AD73422BB-40 Analog Devices Inc, AD73422BB-40 Datasheet - Page 29

• Manufacturer Part Number: AD73422BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occur-
ring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the AD73422. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch either the DMA
4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-
5. Host checks IACK line to see if the DSP has completed the
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
AD73422 is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can, therefore, access a block of sequentially addressed memory
by specifying only the starting address of the block. This in-
creases throughput as the address does not have to be sent for
each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
Once the address is stored, data can either be read from or
written to the AD73422’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the AD73422 that a particular trans-
action is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
additional processor cycle.
REV. 0
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers.
If IAD[15] = 1, the value of IAD[7:0] represents the IDMA
overlay: IAD[14:8] must be set to 0.
If IAD[15] = 0, the value of IAD[13:0] represents the start-
ing address of internal memory to be accessed and IAD[14]
reflects PM or DM for access.
nal memory (PM or DM).
previous IDMA operation.
–29–
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) di-
rects the AD73422 to write the address onto the IAD0–14 bus
into the IDMA Control Register. If IAD[15] is set to 0, IDMA
latches the address. If IAD[15] is set to 1, IDMA latches OVLAY
memory. The IDMA OVLAY and address are stored in separate
memory-mapped registers. The IDMAA register, shown below,
is memory mapped at address DM (0x3FE0). Note that the
latched address (IDMAA) cannot be read back by the host. The
IDMA OVLAY register is memory mapped at address DM
(0x3FE7). See Figure 19 for more information on IDMA and
DMA memory maps.
Bootstrap Loading (Booting)
The AD73422 has two mechanisms to allow automatic loading
of the internal program memory after reset. The method for
booting after reset is controlled by the Mode A, B and C con-
figuration bits.
When the mode pins specify BDMA booting, the AD73422
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
dresses to boot memory must be constructed externally to the
AD73422. The only memory address bit provided by the pro-
cessor is A0.
IDMA Port Booting
The AD73422 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the
AD73422 boots from the IDMA port. IDMA feature can load
as much on-chip memory as desired. Program execution is held
off until on-chip program memory location 0 is written to.
15 14 13 12 11 10 9
U
Figure 19. IDMA Control/OVLAY Registers
IDMAD
DESTINATION MEMORY TYPE:
U
IDMA CONTROL (U = UNDEFINED AT RESET)
0 = PM
1 = DM
U
U
U
U
IDMAA ADDRESS
8
U
U
7
6
U
5
U
4
U
3
U
2
U
AD73422
1
U
0
U
DM(0 3FE0)