SSM2602CPZ-REEL7 Analog Devices Inc, SSM2602CPZ-REEL7 Datasheet
SSM2602CPZ-REEL7
Specifications of SSM2602CPZ-REEL7
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SSM2602CPZ-REEL7 Summary of contents
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... Analog Devices. Trademarks and registered trademarks are the property of their respective owners. GENERAL DESCRIPTION The SSM2602 is a low power, high quality stereo audio codec for portable digital audio applications with one set of stereo programmable gain amplifier (PGA) line inputs and one monaural microphone input ...
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SSM2602 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Digital Filter Characteristics ....................................................... 4 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... ...
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SPECIFICATIONS T = 25°C, AVDD = DVDD = 3.3 V, PVDD = 3 kHz signal Table 1. Parameter RECOMMENDED OPERATING CONDITIONS Analog Voltage Supply (AVDD) Digital Power Supply Ground (AGND, PGND, DGND) POWER CONSUMPTION Power-Up Stereo ...
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SSM2602 Parameter HEADPHONE OUTPUT Full-Scale Output Voltage Maximum Output Power Signal-to-Noise Ratio (A-Weighted) THD + N Power Supply Rejection Ratio Mute Attenuation LINE INPUT TO LINE OUTPUT Full-Scale Output Voltage Signal-to-Noise Ratio (A-Weighted) Total Harmonic Distortion Power Supply Rejection MICROPHONE ...
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TIMING CHARACTERISTICS 2 Table 3. I C® Timing Parameter t MIN t 600 SCS t 600 SCH t 600 SCLK t 100 600 HCS Table 4. ...
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SSM2602 Table 5. Digital Audio Interface Slave Mode Timing Limit Parameter t MIN LRSU t 10 LRH BCH t 25 BCL t 50 BCY Table 6. Digital Audio ...
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Table 7. System Clock Timing Limit Parameter t t MIN MAX t 72 XTIY t 40:60 60:40:00 MCLKDS t 32 XTIH t 32 XTIL t 20 COP t 20 COPDIV2 Unit Description ns MCLK/XTI system clock cycle time MCLK/XTI duty ...
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SSM2602 ABSOLUTE MAXIMUM RATINGS At 25°C, unless otherwise noted. Table 8. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Stresses above those listed under Absolute Maximum ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 10. Pin Function Descriptions Pin No. Mnemonic Type 1 MCLK/XTI Digital Input 2 XTO Digital Output 3 DCVDD Digital Supply 4 DGND Digital Ground 5 DBVDD Digital Supply 6 CLKOUT Digital Output 7 BCLK ...
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SSM2602 TYPICAL PERFORMANCE CHARACTERISTICS CONVERTER FILTER RESPONSE 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.25 0.50 0.75 1.00 1.25 f FREQUENCY ( S Figure 8. ADC Digital Filter Frequency Response 0.05 0.04 0.03 0.02 0.01 ...
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DIGITAL DE-EMPHASIS 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 − FREQUENCY (kHz) Figure 12. De-Emphasis Frequency Response, Audio Sampling Rate = 32 kHz 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0 ...
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SSM2602 THEORY OF OPERATION DIGITAL CORE Inside the SSM2602 digital core is one central clock source, called the master clock (MCLK), that produces a reference clock for all internal audio data processing and synchronization. When using an external clock source ...
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AUTOMATIC LEVEL CONTROL (ALC) The SSM2602 codec has an automatic level control (ALC) that can be activated to suppress clipping and improve dynamic range even if a sudden, loud input signal is introduced. This is achieved by continuously adjusting the ...
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SSM2602 ANALOG INTERFACE Signal Chain The SSM2602 includes stereo single-ended line and monaural microphone inputs to the on-board ADC. Either the line inputs or the microphone input, but not both simultaneously, can be connected to the ADC by setting the ...
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Bypass and Sidetone Paths to Output The line and microphone inputs can be routed and mixed directly to the output terminals via the SIDETONE_EN (Register R4, Bit D5) and BYPASS (Register R4, Bit D3) software control register selections. In both ...
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SSM2602 DIGITAL AUDIO INTERFACE The digital audio input can support the following four digital audio communication protocols: right-justified mode, left-justified mode mode, and digital-signal processor (DSP) mode. The mode selection is performed by writing to the FORMAT ...
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LEFT CHANNEL RECLRC/ PBLRC BCLK RECDAT PBDAT X = DON’T CARE. LEFT CHANNEL RECLRC/ PBLRC BCLK RECDAT PBDAT X = DON’T CARE. LEFT CHANNEL RECLRC/ PBLRC BCLK RECDAT/ PBDAT ...
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SSM2602 SOFTWARE CONTROL INTERFACE The software control interface provides access to the user-selectable control registers and can operate with a 2-wire (I (SPI) interface, depending on the setting of the MODE pin. If the MODE pin is set to 0, ...
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TYPICAL APPLICATION CIRCUITS AVDD MICBIAS RLINEIN MICIN MIC LLINEIN LINE OSC OSC MCLK/XTI XTO Figure 31. SSM2602 Power Management Functional Location Diagram (Control Register R6, Bit D0 to Bit D7 1uF ...
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SSM2602 REGISTER MAP Table 11. Register Map Reg. Address Name D8 R0 0x00 Left-Channel LRINBOTH ADC Input Volume R1 0x01 Right-Channel RLINBOTH ADC Input Volume R2 0x02 Left-Channel LRHPBOTH DAC Volume R3 0x03 Right-Channel RLHPBOTH DAC Volume R4 0x04 Analog ...
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REGISTER MAP DETAILS LEFT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x00 Table 12. Left-Channel ADC Input Volume Register Bit Map D8 D7 LRINBOTH LINMUTE Table 13. Descriptions of Left-Channel ADC Input Volume Register Bits Bit Name Description LRINBOTH Left-to-right line input ADC ...
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SSM2602 RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01 Table 14. Right-Channel ADC Input Volume Register Bit Map D8 D7 RLINBOTH RINMUTE Table 15. Descriptions of Right-Channel ADC Input Volume Register Bits Bit Name Description RLINBOTH Right-to-left line input ADC data load ...
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LEFT-CHANNEL DAC VOLUME, ADDRESS 0x02 Table 16. Left-Channel DAC Volume Register Bit Map D8 D7 LRHPBOTH LZCEN Table 17. Descriptions of Left-Channel DAC Volume Register Bits Bit Name Description LRHPBOTH Left-to-right headphone volume load control LZCEN Left-channel zero cross detect ...
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SSM2602 ANALOG AUDIO PATH, ADDRESS 0x04 Table 20. Analog Audio Path Register Bit Map MICBOOST2 SIDETONE_ATT [1:0] Table 21. Descriptions of Analog Audio Path Register Bits Bit Name Description MICBOOST2 Additional microphone amplifier gain booster control. SIDETONE_ATT ...
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POWER MANAGEMENT, ADDRESS 0x06 Table 24. Power Management Register Bit Map PWROFF CLKOUT Table 25. Description of Power Management Register Bits Bit Name Description PWROFF Whole chip power-down control CLKOUT Clock output power-down control OSC Crystal ...
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SSM2602 DIGITAL AUDIO I/F, ADDRESS 0x07 Table 27. Digital Audio I/F Register Bit Map BCLKINV MS Table 28. Descriptions of Digital Audio I/F Register Bits Bit Name Description BCLKINV BCLK inversion control MS Master mode enable ...
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Table 31. Sampling Rate Lookup Table, USB Disabled (Normal Mode) MCLK (CLKDIV2 = 0) MCLK (CLKDIV2 = 1) 12.288 MHz 24.576 MHz 11.2896 MHz 22.5792 MHz 18.432 MHz 36.864 MHz 16.9344 MHz 33.8688 MHz 1 BCLK frequency is for master ...
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SSM2602 Table 32. Sampling Rate Lookup Table, USB Enabled (USB Mode) MCLK (CLKDIV2 = 0) MCLK (CLKDIV2 = 1) 12.000 MHz 24.000 MHz 1 BCLK frequency is for master mode and slave right-justified mode only. ADC Sampling Rate DAC Sampling ...
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ACTIVE, ADDRESS 0x09 Table 33. Active Register Bit Map Table 34. Descriptions of Active Register Bit Bit Name Description ACTIVE Digital core activation control RESET, ADDRESS 0x0F Table 35. Software Reset Register Bit Map ...
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SSM2602 ALC CONTROL 1, ADDRESS 0x10 Table 37. ALC Control 1 Register Bit Map ALCSEL [1:0] Table 38. Descriptions of ALC Control 1 Register Bits Bit Name Description ALCSEL [1:0] ALC select MAXGAIN [2:0] PGA maximum gain ...
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NOISE GATE, ADDRESS 0x12 Table 41. Noise Gate Register Bit Map Table 42. Descriptions of Noise Gate Register Bits Bit Name Description NGTH [4:0] Noise gate threshold NGG [1:0] Noise gate type NGAT Noise gate control ...
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... Model Temperature Range 1 SSM2602CPZ-R2 −40°C to +85°C SSM2602CPZ-REEL 1 −40°C to +85°C 1 SSM2602CPZ-REEL7 −40°C to +85°C 1 SSM2602-EVALZ RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.00 BSC SQ ...