AD9843AJSTZRL Analog Devices Inc, AD9843AJSTZRL Datasheet - Page 3

• Manufacturer Part Number: AD9843AJSTZRL
• Manufacturer: Analog Devices Inc

Specifications of AD9843AJSTZRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

CCD-MODE SPECIFICATIONS
Parameter
P
MAXIMUM CLOCK RATE
CDS
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
SYSTEM PERFORMANCE
POWER-UP RECOVERY TIME
NOTES
1
Specifications subject to change without notice.
TRANSIENT
Input Signal Characteristics defined as follows, with 4 dB CDS gain:
500mV TYP
OWER CONSUMPTION
Allowable CCD Reset Transient
Max CCD Black Pixel Amplitude
Max Input Range Before Saturation
Max Input Range Before Saturation
Max Input Range Before Saturation
Max Output Range
Gain Resolution
Gain Range (Two’s Complement Coding)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Clamp Level Resolution
Clamp Level
Gain Accuracy, VGA Code 91 to 1023
Peak Nonlinearity, 500 mV Input Signal
Peak Nonlinearity, 800 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
From Fast Recovery Mode
From Reference Standby Mode
From Total Shutdown Mode
From Power-Off Condition
RESET
Min Gain (CDS Gain Register Code 32)
Medium Gain (CDS Gain Code 63)
Max Gain (CDS Gain Code 31)
Low Gain (VGA Register Code 91)
Max Gain (VGA Code 1023)
Min Clamp Level
Max Clamp Level
BLACK PIXEL
200mV MAX
OPTICAL
SIGNAL RANGE
1V MAX
INPUT
1
1
1
(T
Min
20
1.0
1.6
1.6
2.0
–0.5
MIN
to T
MAX
Guaranteed
, AVDD = DVDD = 3.0 V, f
Typ
78
500
200
1.5
0.5
64
–2
4
10
1024
2
36
256
0
63.75
0.1
0.4
0.2
40
0.1
1
3
15
Max
+0.5
Unit
mW
MHz
mV
mV
V p-p
V p-p
V p-p
V p-p
Steps
dB
dB
dB
V p-p
V p-p
Steps
dB
dB
Steps
LSB
LSB
dB
%
%
LSB rms
dB
ms
ms
ms
ms
DATACLK
= f
SHP
See Input Waveform in Note 1
With 4 dB CDS Gain
With –2 dB CDS Gain
With 10 dB CDS Gain
At Any CDS Gain Setting
See Figure 12 for CDS Gain Curve
Use Equations on Page 13 to Calculate Gain
12 dB Gain Applied (4 dB CDS Gain)
8 dB Gain Applied (4 dB CDS Gain)
Measured with Step Change on Supply
Notes
See TPC 1 for Power Curves
4 dB Is Default with CDS Gain Disabled
See Figure 13 for VGA Gain Curve
See Page 13 for Gain Equations
Measured at ADC Output
Specifications Include Entire Signal Chain
AC Grounded Input, 6 dB Gain Applied
Clocks Must Be Applied, as in Figures 5 and 6
= f
SHD
= 20 MHz, unless otherwise noted.)
AD9843A