AD830JRZ-REEL7 Analog Devices Inc, AD830JRZ-REEL7 Datasheet - Page 10

• Manufacturer Part Number: AD830JRZ-REEL7
• Manufacturer: Analog Devices Inc

Specifications of AD830JRZ-REEL7

• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Compliant

AD830
The bandwidth, high impedance, and transient behavior of the
AD830 is symmetrical for both polarities of gain. This is very
advantageous and unlike an op amp.
Input Impedance
The relatively high input impedance of the AD830, for a differ-
ential receiver amplifier, permits connections to modest impedance
sources without much loading or loss of common-mode rejection.
The nominal input resistance is 300 kΩ. The real limit to the
upper value of the source resistance is in its effect on common-
mode rejection and bandwidth. If the source resistance is in
only one input, then the low frequency common-mode rejection
will be lowered to ≈ R
tance pole
limits the bandwidth.
Furthermore, the high frequency common-mode rejection will
be additionally lowered by the difference in the frequency
response caused by the R
good low and high frequency common-mode rejection, it is
recommended that the source resistances of the + and – inputs
be matched and of modest value (≤10 kΩ).
Handling Bias Currents
The bias currents are typically 4 µA flowing into each pin of the
G
finite source resistance, the bias current through this resistor
will create a voltage drop (I
impedance of the AD830 permits modest values of R
≤10 kΩ. If the source resistance is in only one terminal, then an
objectional offset voltage may result (e.g., 4 µA × 5 kΩ = 20 mV).
Placement of an equal value resistor in series with the other input
will cancel the offset to first order. However, due to mismatches
in the resistances, a residual offset will remain and likely be
greater than the bias current (offset current) mismatches.
Applying Feedback
The AD830 is intended for use with gains from 1 to 100. Gains
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 21) with gain >1.
The value of the bottom resistor R
to ensure that the pole formed by C
tion of R
not introduce excessive phase shift around the loop and destabi-
lize the amplifier. A compensating resistor, equal to the parallel
combination of R
other Y G
mode rejection and to lower the offset voltage induced by the
input bias current.
Output Common Mode
The output swing of the AD830 is defined by the differential
input voltage, the gain, and the output common. Depending on
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output voltage
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus the supply is
shown in Figure 12. A prediction of the common-mode range
M
stages of the AD830. Since all applications possess some
1
M
and R
stage input to preserve the high frequency common-
2
1
is sufficiently high in frequency so that it does
and R


IN
f
/R
2
=
S
, should be placed in series with the
S
× C
. The source resistance/input capaci-
2π
BIAS
1
IN
×
× R
R
pole. Therefore, to maintain
2
S
should be kept less than 1 kΩ
S
IN
×
). The relatively high input
C
and the parallel connec-
IN


S
, typically
–10–
versus the peak output differential voltage can be easily derived
from the maximum output swing as V
Output Current
The absolute peak output current is set by the short-circuit
current limiting, typically greater than 60 mA. The maximum
drive capability is rated at 50 mA, but without a guarantee of
distortion performance. Best distortion performance is obtained
by keeping the output current ≤20 mA. Attempting to drive
large voltages into low valued resistances (e.g., 10 V into 150 Ω)
will cause an apparent lowering of the limit for output signal
swing but is just the current limiting behavior.
Driving Cap Loads
The AD830 is capable of driving modest sized capacitive loads
while maintaining its rated performance. Several curves of
bandwidth versus capacitive load are given in TPCs 15 and 18.
The AD830 was designed primarily as a low distortion video
speed amplifier, but with a trade-off, i.e., giving up very large
capacitive load driving capability. If very large capacitive loads
must be driven, the network shown in Figure 13 should be used
to ensure stable operation. If the loss of gain caused by the
resistor R
optional feedback network shown may be added to restore the
lost gain.
V
CM
Figure 13. Circuit for Driving Large Capacitive Loads
Z
CM
Figure 12. Maximum Output Swing vs. Supply
SIGNAL
INPUT
15
12
9
6
3
0
S
0
in series with the load is objectionable, the
1
2
3
4
G
G
4
M
M
SUPPLY VOLTAGE – V
8
C
AD830
A = 1
V
P
OCM
12
8
7
6
5
+V
= V
V
S
0.1 F
0.1 F
–V
N
S
MAX
16
100pF
– V
36.5
R
S
C
PEAK
1
*OPTIONAL
R
R
FEEDBACK
NETWORK
S
2
REV. B
20
V
OUT
.
R
1k
1