LMF90CCWM National Semiconductor, LMF90CCWM Datasheet - Page 10

• Manufacturer Part Number: LMF90CCWM
• Manufacturer: National Semiconductor

Specifications of LMF90CCWM

• Architecture: Switched Capacitor
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): ±3/±5V
• Power Supply Requirement: Single/Dual
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

Pin Descriptions
W (Pin 1)
R (Pin 2)
LD (Pin 3)
XTAL2 (Pin 4) This is the output of the internal crystal os-
XTAL1 (Pin 5) This is the crystal oscillator input When us-
CLK (Pin 6)
XLS (Pin 7)
1 ) When W is tied to V
This three-level logic input sets the width of
the notch Notch width is f
13) or V
0 26 f
This three-level logic input sets the ratio of
the clock frequency (f
quency (f
V
33 33 1 50 1 or 100 1 respectively
This three-level logic input sets the division
factor of the clock frequency divider When
LD is tied to V
factor is 716 596 or 2 respectively
cillator When using the internal oscillator
the crystal should be tied between XTAL2
and XTAL1 (The capacitors are internal
no external capacitors are needed for the
oscillator to operate ) When not using the
internal oscillator this pin should be left
open
ing the internal oscillator the crystal should
be tied between XTAL1 and XTAL2 XTAL1
can also be used as an input for an external
clock signal swinging from V
frequency of the crystal or the external
clock will be divided internally by the clock
divider as determined by the programming
voltage on pin 3
This is the filter clock pin The clock signal
appearing on this pin is the filter clock
(f
lator or an external clock signal applied to
pin 5 while pin 7 is tied to V
the output of the divider and can be used to
drive other LMF90s with its rail-to-rail output
swing When not using the internal crystal
oscillator or an external clock on pin 5 the
CLK pin can be used as a CMOS or TTL
clock input provided that pin 7 is tied to
GND or V
cycle of a clock signal applied to this pin
should be near 50% especially at higher
clock frequencies
This is a three-level logic pin When XLS is
tied to V
quency divider are enabled and CLK (pin 6)
is an output When XLS is tied to GND (pin
13) the crystal oscillator and frequency di-
vider are disabled and pin 6 is an input for a
clock swinging between V
XLS is tied to V
frequency divider are disabled and pin 6 is a
TTL level clock input for a clock signal
swinging between GND and V
V
CLK
b
b
and GND
) When using the internal crystal oscil-
the clock-to-center-frequency ratio is
0
or 0 127 f
b
0
a
b
) When R is tied to V
(pin 8) the notch width is 0 55 f
For best performance the duty
the crystal oscillator and fre-
a
b
0
GND or V
the crystal oscillator and
respectively
CLK
a
) to the center fre-
c2
(pin 14) GND (pin
b
a
– f
and V
b
a
c1
the CLK pin is
a
a
to V
the division
(see Figure
or between
a
GND or
b
When
The
0
10
V
V
D (Pin 10)
V
V
GND (Pin 13)
V
1 0 Definition of Terms
A
ter’s passband (See Figure 1 ) For the LMF90 A
nominally equal to 0 25 dB
A
(See Figure 1 ) This parameter is adjusted by programming
voltage applied to pin 10 (D)
Bandwidth (BW) or Passband Width the difference in fre-
quency between the notch filter’s two cutoff frequencies
Cutoff Frequency for a notch filter one of the two fre-
quencies f
band At these two frequencies the filter has a gain equal to
the passband gain
f
CLK pin This frequency determines the filter’s center fre-
quency Depending on the programming voltage on pin 2
(R) f
frequency of the notch
f
frequency is measured by finding the two frequencies for
which the gain
calculating their geometrical mean
Passband for a notch filter frequencies above the upper
cutoff frequency (f
frequency (f
CLK
0
OUT
IN2
IN1
b
a
max
min
or f
(Pin 8)
(Pin 14)
(Pin 11)
(Pin 12)
CLK
(Pin 9)
the minimum attenuation within the notch’s stopband
the frequency of the clock signal that appears at the
the maximum amount of gain variation within the fil-
Notch
will be either 33 33 50 or 100 times the center
C1
C1
the center frequency of the notch filter This
and f
in Figure 1 )
b
This is the negative power supply pin It
should be bypassed with at least a 0 1 F
capacitor
connect this pin to system ground
This is the filter output
This two-level logic input is used to set the
depth of the notch (the attenuation at f
When D is tied to GND or V
notch depth is 48 dB or 39 dB respective-
ly Note however that the notch depth is
also dependent on the width setting (pin
1) See the Electrical Characteristics for
tested limits
This is the input to the difference amplifier
section of the notch filter
This is the input to the internal bandpass
filter This pin is normally connected to pin
11 For wide bandwidth applications an
anti-aliasing filter can be inserted between
pin 11 and pin 12
This is the analog ground reference for the
LMF90 In split supply applications GND
should be connected to the system
ground When operating the LMF90 from a
single positive power supply voltage pin
13 should be connected to a ‘‘clean’’ refer-
ence voltage midway between V
V
This is the positive power supply pin It
should be bypassed with at least a 0 1 F
capacitor
C2
3 dB relative to the passband gain and
b
C2
in Figure 1 ) and below the lower cutoff
that define the edges of the pass-
For single-supply operation
b
the typical
a
Max
and
0
is
)