ADV7175AKSZ Analog Devices Inc, ADV7175AKSZ Datasheet - Page 24

• Manufacturer Part Number: ADV7175AKSZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7175AKSZ

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

ADV7175A/ADV7176A
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 33 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Selection (MR12–MR11)
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
DAC Control (MR16–MR13)
These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7175A/
ADV7176A if any of the DACs are not required in the application.
Color Bar Control (MR17)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7175A/ADV7176A is
configured in a master timing mode as per the one selected by
bits TR01 and TR02.
SUBCARRIER FREQUENCY REGISTER 3-0
(FSC3–FSC0)
(Address [SR4–SR0] = 05H–02H)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers are calculated by using
the following equation:
Subcarrier Frequency Register =
i.e.: NTSC Mode,
Subcarrier Frequency Value =
Figure 34 shows how the frequency is set up by the four registers.
F
F
CLK
SCF
= 3.5795454 MHz
= 27 MHz,
= 21F07C16 HEX
REGISTER RESET
TR07
TIMING
TR07
27 ×10
2
2
F
32
TR06
32
CLK
PIXEL PORT
0
1
CONTROL
–1
–1
6
TR06
× F
8-BIT
16-BIT
× 3.5795454 ×10
SCF
TR05 TR04
TR05
0
0
1
1
LUMA DELAY
0
1
0
1
6
TR04
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
TR03
BLANK INPUT
0
1
CONTROL
TR03
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 06H)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°.
TIMING REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)
Figure 35 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7175A/ADV7176A is in
master or slave mode.
Timing Mode Selection (TR02–TR01)
These bits control the timing mode of the ADV7175A/
ADV7176A. These modes are described in the Timing and
Control section of the data sheet.
BLANK Input Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode.
Luma Delay (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Control (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on Pins
P7–P0.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
ENABLE
DISABLE
SUBCARRIER
SUBCARRIER
SUBCARRIER
SUBCARRIER
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
TR02 TR01
0
0
1
1
REG 3
REG 2
REG 1
REG 0
TIMING MODE
TR02
SELECTION
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
FSC23
FSC15
FSC31
FSC7
TR01
TR00
FSC22 FSC21
FSC14 FSC13
FSC30 FSC29
FSC6
0
1
MASTER/SLAVE
CONTROL
SLAVE TIMING
MASTER TIMING
TR00
FSC5
FSC20
FSC12
FSC28
FSC4
FSC19
FSC11
FSC27
FSC3
FSC10
FSC18
FSC26
FSC2
FSC25
FSC17
FSC1
FSC9
FSC24
FSC16
FSC8
FSC0