ADV7310KSTZ Analog Devices Inc, ADV7310KSTZ Datasheet - Page 35
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ADV7310KSTZ
Manufacturer Part Number
ADV7310KSTZ
Description
Manufacturer
Analog Devices Inc
Datasheet
1.ADV7310KSTZ.pdf
(84 pages)
Specifications of ADV7310KSTZ
Number Of Dac's
6
Adc/dac Resolution
12b
Screening Level
Commercial
Package Type
LQFP
Pin Count
64
Lead Free Status / RoHS Status
Compliant
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P_HSYNC
1 → 0
0
0 → 1
1
1
*When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 14h, Bit 0] from 0 to 1. In this state the horizontal
and vertical counters will remain reset. When this bit is set back
to 0, the internal counters will commence counting again.
REV. A
P_VSYNC
0
0 → 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0
0 → 1
1 → 0
P_BLANK*
Table V. Async Timing Mode Truth Table
Reference
50% point of falling edge of trilevel horizontal sync signal
25% point of rising edge of trilevel horizontal sync signal
50% point of falling edge of trilevel horizontal sync signal
50% start of active video
50% end of active video
–35–
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
ADV7310/ADV7311
in Figure 29
Reference
a
b
c
d
e
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