ADV7190KST Analog Devices Inc, ADV7190KST Datasheet - Page 19

• Manufacturer Part Number: ADV7190KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7190KST

• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

Vertical Blanking Data Insertion and BLANK Input
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not have line sync or pre-/post-
equalization pulses (see Figures 34 to 45). This mode of operation
is called Partial Blanking. It allows the insertion of any VBI
data (Opened VBI) into the encoded output waveform. This data
is present in digitized incoming YCbCr data stream (e.g., WSS
data, CGMS, VPS etc.). Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines. VBI is available
in all timing modes.
It is possible to allow control over the BLANK signal using Timing
Register 0. When the BLANK input is enabled (TR03 = 0 and
input pin tied low), the BLANK input can be used to input
externally generated blank signals in Slave Mode 1, 2, or 3. When
the BLANK input is disabled (TR03 = 1 and input pin tied low
or tied high), the BLANK input is not used and the ADV7190/
ADV7191 automatically blanks all normally blank lines as per
CCIR-624. (Timing Register 0.)
YUV Levels
This functionality allows the ADV7190/ADV7191 to output
SMPTE levels or Betacam levels on the Y output when config-
ured in PAL or NTSC mode.
Betacam
SMPTE
MII
As the data path is branched at the output of the filters the luma
signal relating to the CVBS or S-Video Y/C output is unaltered.
It is only the Y output of the YCrCb outputs that is scaled.
This control allows color component levels to have a peak-peak
amplitude of 700 mV, 1000 mV or the default values of 934 mV
in NTSC and 700 mV in PAL. (Mode Register 5.)
16-Bit Interface
It is possible to input data in 16-bit format. In this case, the
interface only operates if the data is accompanied by separate
HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not avail-
able in Slave Mode 0 since EAV/SAV timing codes are used.
(Mode Register 8.)
4
It is possible to operate all six DACs at 27 MHz (2¥ Oversam-
pling) or 54 MHz (4¥ Oversampling).
The ADV7190/ADV7191 is supplied with a 27 MHz clock synced
with the incoming data. Two options are available: to run the
device throughout at 27 MHz or to enable the PLL. In the latter
case, even if the incoming data runs at 27 MHz, 4¥ Oversam-
pling and the internal PLL will output the data at 54 MHz.
NOTE
In 4¥ Oversampling Mode the requirements for the optional
output filters are different from those in 2¥ Oversampling. (Mode
Register 1, Mode Register 6.) See Appendix 6 for further details.
REV. B
Oversampling and Internal PLL
Sync
286 mV
300 mV
300 mV
Video
714 mV
700 mV
700 mV
–19–
VIDEO TIMING DESCRIPTION
The ADV7190/ADV7191 is intended to interface to off-the-
shelf MPEG1 and MPEG2 Decoders. As a consequence, the
ADV7190/ADV7191 accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 Pixel Port and has several Video Timing Modes of
operation that allow it to be configured as either System Master
Video Timing Generator or a Slave to the System Video Timing
Generator. The ADV7190/ADV7191 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
The ADV7190/ADV7191 calculates the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.
In addition, the ADV7190/ADV7191 supports a PAL or NTSC
square pixel operation. The part requires an input pixel clock of
24.5454 MHz for NTSC square pixel operation and an input
pixel clock of 29.5 MHz for PAL square pixel operation. The
internal horizontal line counters place the various video waveform
sections in the correct location for the new clock frequencies.
The ADV7190/ADV7191 has four distinct Master and four distinct
Slave timing configurations. Timing Control is established with
the bidirectional HSYNC, BLANK, and VSYNC pins. Timing
Register 1 can also be used to vary the timing pulsewidths and
where they occur in relation to each other. (Mode Register 2,
Timing Register 0, 1.)
RESET SEQUENCE
When RESET becomes active the ADV7190/ADV7191 reverts to
the default output configuration (see Appendix 8 for register
settings). The ADV7190/ADV7191 internal timing is under the
control of the logic level on the NTSC_PAL pin.
MPEG2
Figure 30. PLL and 4
6.75
PIXEL BUS
27MHz
REQUIREMENTS
2
13.5
FILTER
ADV7190/ADV7191
ENCODER
PLL
CORE
ENCODER
FREQUENCY – MHz
54MHz
Oversampling Block Diagram
ADV7190/ADV7191
27.0
2
N
E
R
P
O
A
O
N
T
L
T
I
I
REQUIREMENTS
4
FILTER
6
D
A
C
40.5
O
U
T
P
U
T
S
54MHz
OUTPUT
54.0