PC16550DVX National Semiconductor, PC16550DVX Datasheet - Page 4

• Manufacturer Part Number: PC16550DVX
• Manufacturer: National Semiconductor

Specifications of PC16550DVX

• Transmit Fifo: 16Byte
• Receive Fifo: 16Byte
• Transmitter And Receiver Fifo Counter: Yes
• Operating Supply Voltage (typ): 5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

3 0 AC Electrical Characteristics
Note 1 Applicable only when ADS is tied low
Note 2 In the FIFO mode (FCR0
will be delayed 3 RCLKs Status indicators (PE FE BI) will be delayed 3 RCLKs after the first byte has been received For subsequently received bytes these
indicators will be updated immediately after RDRBR goes inactive Timeout interrupt is delayed 8 RCLKs
Note 3 Charge and discharge time is determined by V
Note 4 These specifications are preliminary
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
WC
Baud Generator
N
t
t
t
t
Receiver
t
t
t
t
t
ADS
AH
AR
AS
AW
CH
CS
CSR
CSW
DH
DS
HZ
MR
RA
RC
RCS
RD
RDD
RVD
WA
WC
WCS
WR
XH
XL
BHD
BLD
HW
LW
RAI
RINT
RXI
SCD
SINT
Address Strobe Width
Address Hold Time
RD RD Delay from Address
Address Setup Time
WR WR Delay from Address
Chip Select Hold Time
Chip Select Setup Time
RD RD Delay from Chip Select
WR WR Delay from Select
Data Hold Time
Data Setup Time
RD RD to Floating Data Delay
Master Reset Pulse Width
Address Hold Time from RD RD
Read Cycle Delay
Chip Select Hold Time from RD RD
RD RD Strobe Width
RD RD to Driver Enable Disable
Delay from RD RD to Data
Address Hold Time from WR WR
Write Cycle Delay
Chip Select Hold Time from WR WR
WR WR Strobe Width
Duration of Clock High Pulse
Duration of Clock Low Pulse
Read Cycle
Write Cycle
Baud Divisor
Baud Output Positive Edge Delay
Baud Output Negative Edge Delay
Baud Output Up Time
Baud Output Down Time
Delay from Active Edge
of RD to Reset Interrupt
Delay from RD RD
(RD RBR or RD LSR)
to Reset Interrupt
Delay from RD RBR
to RXRDY Inactive
Delay from RCLK to Sample Time
Delay from Stop to Set Interrupt
e
1) the trigger level interrupts the receiver data available indication the active RXRDY indication and the overrun error indication
e
e
Parameter
t
t
AW
AR
a
a
t
t
RD
WR
a
a
OL
t
RC
t
WC
V
OH
and the external loading
T
A
External Clock (8 Max )
External Clock (8 Max )
f
f
e
X
X
100 pF loading (Note 3)
100 pF loading (Note 3)
e
e
4
0 C to
8
8
100 pF loading
100 pF Load
100 pF Load
100 pF Load
Conditions
d
d
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
a
2 100 pF Load
2 100 pF Load
70 C V
DD
e a
5V
g
5000
Min
125
125
150
100
280
280
100
10%
60
30
60
30
60
30
30
30
30
20
20
20
20
55
55
75
0
0
0
1
2
1000
2000
Max
16
100
175
175
290
60
60
1
b
1
Cycles
RCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns