XR16V794IV-0B-EVB Exar Corporation, XR16V794IV-0B-EVB Datasheet - Page 14

• Manufacturer Part Number: XR16V794IV-0B-EVB
• Description: Supports V794 64 Ld TQFP,ISA Interface
• Manufacturer: Exar Corporation

Specifications of XR16V794IV-0B-EVB

• Design Resources: XR17V798/794 Eval Board Schematic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
When software flow control is enabled (
characters with the programmed Xon-1,2 or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed Xoff-1,2 value(s), the 794 will halt transmission (TX) as soon as the current character has
completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the
interrupt output pin will be activated. Following a suspension due to a match of the Xoff character(s), the 794
will monitor the receive data stream for a match to the Xon-1,2 character(s). If a match is found, the 794 will
resume operation and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon1, Xon2, Xoff1 and Xoff2 flow control registers to ’0’. Following reset,
any desired Xon/Xoff value can be used for software flow control. Different conditions can be set to detect Xon/
Xoff characters (
are selected, the 794 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
F
2.11
IGURE
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
9. A
Auto Xon/Xoff (Software) Flow Control
(RXA FIFO
CTSB#
RXA FIFO
Interrupt)
RTSA#
TXB
INTA
UTO
Trigger Reached
Receiver FIFO
Trigger Level
Local UART
Transmitter
Auto CTS
Auto RTS
RTS/DTR
See Table 18
UARTA
Monitor
Data Starts
Receive
Data
Assert RTS# to Begin
AND
1
2
Transmission
Trigger Level
) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
3
4
RX FIFO
CTS/DSR F
RTSA#
TXA
CTSA#
RXA
ON
ON
See Table 18
LOW
5
C
7
Threshold
RTS High
ONTROL
), the 794 compares one or two sequential receive data
14
6
8
O
OFF
Suspend
PERATION
OFF
RTSB#
CTSB#
Threshold
RTS Low
RXB
TXB
Restart
9
10
11
Trigger Reached
Remote UART
ON
Trigger Level
Receiver FIFO
12
Auto CTS
Auto RTS
Transmitter
UARTB
Monitor
ON
Trigger Level
RX FIFO
RTSCTS1
REV. 1.0.1