SY89467UHY Micrel Inc, SY89467UHY Datasheet - Page 7

• Manufacturer Part Number: SY89467UHY
• Description: 1:20 LVPECL Fanout W/ 2:1 FSI Input MUX
• Manufacturer: Micrel Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: Precision Edge®r

Specifications of SY89467UHY

• Number Of Circuits: 1
• Ratio - Input:output: 2:20
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, PECL
• Output: LVPECL
• Frequency - Max: 2GHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Frequency-max: 2GHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 2000MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Package Type: TQFP EP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/PECL
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2085; SY89467UHY

Functional Description
Clock Select (SEL)
SEL is an asynchronous TTL/CMOS compatible input
that selects one of the two input signals. An internal
25kΩ pull-up resistor defaults the input to logic HIGH if
left open. Input switching threshold is V
Figure 1a.
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below
frequency of the SY89467U is limited by the FSI
function. Refer to Figure 1b.
Micrel, Inc.
April 2008
100mV
PK
,
typically
30mV
PK
CC
.
/2. Refer to
Maximum
7
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing such that the voltage across the input
pair is significantly less than 100mV, FSI function will
eliminate a metastable condition and latch the outputs
to the last valid state. No ringing and no undetermined
state will occur at the output under these conditions.
The output recovers to normal operation once the
input signal returns to a valid state with a typical swing
greater than 30mV.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on the rise and fall time
of the input signal and on its amplitude.
Output Enable (OE)
OE is a synchronous TTL/CMOS compatible input that
enables/disables the outputs based upon the input to
this pin. The enable function is synchronous so that
the clock outputs will be enabled or disabled following
a rising and a falling edge of the input clock. Refer to
Figure 1c. Internal 25kΩ pull-up resistor defaults the
input to logic HIGH if left open. Input switching
threshold is V
CC
/2.
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M9999-040808-C
SY89467U