STM8AF6268TDX STMicroelectronics, STM8AF6268TDX Datasheet - Page 43

• Manufacturer Part Number: STM8AF6268TDX
• Description: 8 BITS MICROCONTR
• Manufacturer: STMicroelectronics
• Series: STM8Ar

Specifications of STM8AF6268TDX

• Core Processor: STM8A
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 32-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM8AF61xx, STM8AF62xx
9
Table 17.
Addr.
480A
0x00
4800
0x00
4801
0x00
4802
0x00
4803
0x00
4804
0x00
4805
0x00
4806
0x00
4807
0x00
4808
0x00
4809
0x00
remapping
HSE clock
protection
Watchdog
User boot
Read-out
Alternate
function
Option
startup
(ROP)
(UBC)
option
option
name
(AFR)
Clock
code
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be toggled in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Option bytes
byte no.
NOPT1
NOPT2
NOPT3
NOPT4
NOPT5
Option
OPT0
OPT1
OPT2
OPT3
OPT4
OPT5
Table 17: Option bytes
NAFR
AFR7
7
7
Reserved
Reserved
Reserved
Reserved
NAFR
AFR6
6
6
Reserved
Reserved
Doc ID 14952 Rev 5
NAFR
AFR5
below.
5
5
N16MHZ
16MHZ
TRIM0
TRIM0
NAFR
AFR4
NHSECNT[7:0]
4
4
HSECNT[7:0]
Option bits
ROP[7:0]
NAFR
NEXT
AFR3
NLSI
_EN
_EN
EXT
CLK
CLK
LSI
3
3
NUBC[5:0]
UBC[5:0]
CKAWU
NCKAW
NIWDG
NAFR
IWDG
AFR2
USEL
_HW
_HW
SEL
2
2
WWDG
NWWD
G_HW
NAFR
AFR1
_HW
NPR
PRS
SC1
C1
1
1
WWDG
NWWG
_HALT
_HALT
NAFR
AFR0
PRS
NPR
SC0
C0
Option bytes
0
0
Factory
default
setting
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
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