STK22C48-NF25TR Cypress Semiconductor Corp, STK22C48-NF25TR Datasheet - Page 5

• Manufacturer Part Number: STK22C48-NF25TR
• Description: STK22C48-NF25TR
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK22C48-NF25TR

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 16K (2K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Word Size: 8b
• Organization: 2Kx8
• Density: 16Kb
• Interface Type: Parallel
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Surface Mount
• Supply Current: 85mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hardware STORE (HSB) Operation
The STK22C48 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the STK22C48 conditionally initiates a STORE operation
after t
SRAM takes place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress. Pull-up this pin with an external
10 K ohm resistor to V
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the STK22C48 continues SRAM operations for t
t
in progress when HSB is pulled LOW, it allows a time, t
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated,
the STK22C48 continues to drive the HSB pin LOW, releasing it
only when the STORE is complete. After completing the STORE
operation, the STK22C48 remains disabled until the HSB pin
returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power-up or after any low power condition (V
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
Document Number: 001-51000 Rev. *D
DELAY
RESET
DELAY
, multiple SRAM Read operations take place. If a Write is
), an internal RECALL request is latched. When V
. An actual STORE cycle only begins if a Write to the
Figure 3. AutoStore Inhibit Mode
CAP
if HSB is used as a driver.
HRECALL
SWITCH
DELAY
to complete.
, a RECALL
. During
DELAY
CC
CC
to
<
Data Protection
The STK22C48 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when V
less than V
and WE are low) at power-up after a RECALL or after a STORE,
the Write is inhibited until a negative transition on CE or WE is
detected. This protects against inadvertent writes during
power-up or brown out conditions.
Noise Considerations
The STK22C48 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK22C48 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage
conditions. When V
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying V
V
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK22C48 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
I
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5 V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK22C48
depends on the following items:
■
■
■
■
■
■
■
CC
CAP
The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of Reads to Writes
CMOS versus TTL input levels
The operating temperature
The V
I/O loading
. This is the AutoStore Inhibit mode; in this mode, STOREs
and Read or Write cycle time. Worst case current
CC
CC
SWITCH
level
Figure 4 on page 6
and V
. If the STK22C48 is in a Write mode (both CE
CAP
SS,
<V
using leads and traces that are as short
SWITCH
CC
shows the relationship between
, all externally initiated STORE
to ground and applying +5 V to
STK22C48
Page 5 of 17
CC
is
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