SST49LF008A-33-4C-EIE-T Microchip Technology, SST49LF008A-33-4C-EIE-T Datasheet - Page 11

• Manufacturer Part Number: SST49LF008A-33-4C-EIE-T
• Description: 3.0V To 3.6V 8Mbit LPC Firmware Flash 40 TSOP 10x20 Mm T/R
• Manufacturer: Microchip Technology

Specifications of SST49LF008A-33-4C-EIE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 40-TFSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8 Mbit Firmware Hub
SST49LF008A
DESIGN CONSIDERATIONS
SST recommends a high frequency 0.1 µF ceramic capacitor
to be placed as close as possible between V
than 1 cm away from the V
low frequency 4.7 µF electrolytic capacitor from V
should be placed within 1 cm of the V
socket for programming purposes add an additional 1-10 µF
next to each socket.
The RST# pin must remain stable at V
tion of an Erase operation. WP# must remain stable at V
the entire duration of the Erase and Program operations for
non-Boot Block sectors. To write data to the top Boot Block
sectors, the TBL# pin must also remain stable at V
entire duration of the Erase and Program operations.
PRODUCT IDENTIFICATION
The product identification mode identifies the device as the
SST49LF008A and manufacturer as SST.
TABLE 2: Product Identification
MODE SELECTION
The SST49LF008A flash memory devices can operate in
two distinct interface modes: the Firmware Hub Interface
(FWH) mode and the Parallel Programming (PP) mode.
The IC (Interface Configuration pin) is used to set the
interface mode selection. If the IC pin is set to logic High,
the device is in PP mode; while if the IC pin is set Low,
the device is in the FWH mode. The IC selection pin must
be configured prior to device operation. The IC pin is
internally pulled down if the pin is not connected. In FWH
©2006 Silicon Storage Technology, Inc.
Manufacturer’s ID
Device ID
SST49LF008A
0000H
0001H
Byte
DD
pin of the device. Additionally, a
Data
BFH
5AH
IH
DD
for the entire dura-
pin. If you use a
DD
FFBC0000H
FFBC0001H
JEDEC ID
Location
Address
and V
DD
IH
T2.7 1161
SS
to V
for the
IH
less
for
SS
11
mode, the device is configured to interface with its host
using Intel’s Firmware Hub proprietary protocol. Commu-
nication between Host and the SST49LF008A occurs via
the 4-bit I/O communication signals, FWH [3:0] and the
FWH4. In PP mode, the device is programmed via an 11-
bit address and an 8-bit data I/O parallel signals. The
address inputs are multiplexed in row and column
selected by control signal R/C# pin. The column
addresses are mapped to the higher internal addresses,
and the row addresses are mapped to the lower internal
addresses. See the Device Memory Map in Figure 5 for
address assignments.
FIRMWARE HUB (FWH) MODE
Device Operation
The FWH mode uses a 5-signal communication interface,
FWH[3:0] and FWH4, to control operations of the
SST49LF008A. Operations such as Memory Read and
Memory Write uses Intel FWH propriety protocol. JEDEC
Standard SDP (Software Data Protection) Byte-Program,
Sector-Erase and Block-Erase command sequences are
incorporated into the FWH memory cycles. Chip-Erase is
only available in PP Mode.
The device enters standby mode when FWH4 is high and
no internal operation is in progress. The device is in ready
mode when FWH4 is low and no activity is on the FWH bus.
Firmware Hub Interface Cycles
Addresses and data are transferred to and from the
SST49LF008A by a series of “fields,” where each field con-
tains 4 bits of data. SST49LF008A supports only single-
byte Read and Write, and all fields are one clock cycle in
length. Field sequences and contents are strictly defined
for Read and Write operations. Addresses in this section
refer to addresses as seen from the SST49LF008A’s “point
of view,” some calculation will be required to translate these
to the actual locations in the memory map (and vice versa)
if multiple memory devices are used on the bus. Tables 3
and 4 list the field sequences for Read and Write cycles.
S71161-11-000
Data Sheet
3/06