SST39VF400A-70-4C-MAQE-T Microchip Technology, SST39VF400A-70-4C-MAQE-T Datasheet - Page 8

• Manufacturer Part Number: SST39VF400A-70-4C-MAQE-T
• Description: 2.7V To 3.6V 4Mbit Multi-Purpose Flash 48 WFBGA 4x6x0.8 Mm T/R
• Manufacturer: Microchip Technology
• Series: -r

Specifications of SST39VF400A-70-4C-MAQE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (256K x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-WFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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© 2011 Silicon Storage Technology, Inc.
Write Operation Status Detection
Data# Polling (DQ
Toggle Bit (DQ
Data Protection
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the ris-
ing edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid
read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing dia-
gram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide two software means to detect
the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data# Polling (DQ
Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the write cycle, otherwise the rejection is valid.
When the SST39LF200A/400A/800A and SST39VF200A/400A/800A are in the internal Program oper-
ation, any attempt to read DQ
ation is completed, DQ
immediately following the completion of an internal Write operation, the remaining data outputs may
still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after
an interval of 1 µs. During internal Erase operation, any attempt to read DQ
the internal Erase operation is completed, DQ
rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling
timing diagram and Figure 19 for a flowchart.
During the internal Program or Erase operation, any consecutive attempts to read DQ
alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is
completed, the DQ
Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-
or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 19 for a flowchart.
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
7
or DQ
6
)
7
6
)
. In order to prevent spurious rejection, if an erroneous result occurs, the software
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
6
bit will stop toggling. The device is then ready for the next operation. The Toggle
SST39VF200A / SST39VF400A / SST39VF800A
7
SST39LF200A / SST39LF400A / SST39LF800A
will produce true data. Note that even though DQ
7
will produce the complement of the true data. Once the Program oper-
8
7
will produce a ‘1’. The Data# Polling is valid after the
7
) and Toggle Bit (DQ
7
will produce a ‘0’. Once
7
may have valid data
DS25001A
6
6
). The End-of-
will produce
Data Sheet
03/11