SST39VF3201-70-4I-B3KE Microchip Technology, SST39VF3201-70-4I-B3KE Datasheet - Page 4

• Manufacturer Part Number: SST39VF3201-70-4I-B3KE
• Description: 2.7V To 3.6V 32Mbit Multi-Purpose Flash 48 TFBGA 6x8x1.2 Mm TRAY
• Manufacturer: Microchip Technology

Specifications of SST39VF3201-70-4I-B3KE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (2M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Data Protection
The SST39VF160x/320x provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST39VF1602/3202 support top hardware block pro-
tection, which protects the top 32 KWord block of the
device. The SST39VF1601/3201 support bottom hardware
block protection, which protects the bottom 32 KWord block
of the device. The Boot Block address ranges are
described in Table 2. Program and Erase operations are
prevented on the 32 KWord when WP# is low. If WP# is left
floating, it is internally held high via a pull-up resistor, and
the Boot Block is unprotected, enabling Program and
Erase operations on that block.
TABLE 2: Boot Block Address Ranges
©2008 Silicon Storage Technology, Inc.
Product
Bottom Boot Block
Top Boot Block
DD
SST39VF1601/3201
SST39VF1602
SST39VF3202
Power Up/Down Detection: The Write operation is
DD
is less than 1.5V.
0F8000H-0FFFFFH
1F8000H-1FFFFFH
000000H-007FFFH
Address Range
T2.0 1223
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
4
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
required after RST# is driven high before a valid Read can
take place (see Figure 16).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF160x/320x provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
6 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to read mode within T
can be V
mand sequence.
Common Flash Memory Interface (CFI)
The SST39VF160x/320x also contain the CFI information
to describe the characteristics of the device. In order to
enter the CFI Query mode, the system must write three-
byte sequence, same as product ID entry command with
98H (CFI Query command) to address 5555H in the last
byte sequence. Once the device enters the CFI Query
mode, the system can read CFI data at the addresses
given in Tables 7 through 10. The system must write the
CFI Exit command to return to Read mode from the CFI
Query mode.
IL
or V
RP ,
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
IH
any in-progress operation will terminate and
, but no other value, during any SDP com-
RC.
The contents of DQ
S71223-05-000
15
RHR
-DQ
6/08
is
8