SST39VF1602C-70-4I-EKE Microchip Technology, SST39VF1602C-70-4I-EKE Datasheet - Page 4

• Manufacturer Part Number: SST39VF1602C-70-4I-EKE
• Description: 2.7V To 3.6V 16Mbit Multi-Purpose Flash 48 TSOP 12x20 Mm TRAY
• Manufacturer: Microchip Technology

Specifications of SST39VF1602C-70-4I-EKE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and ‘0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ
An additional Toggle Bit is available on DQ
used in conjunction with DQ
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ
pulse of Write operation. See Figure 10 for Toggle Bit tim-
ing diagram and Figure 23 for a flowchart.
TABLE 1: Write Operation Status
Note: DQ
Data Protection
The SST39VF1601C/1602C provide both hardware and
software features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
inhibited when V
©2010 Silicon Storage Technology, Inc.
Status
Normal
Operation
Erase-
Suspend
Mode
DD
6
2
will be set to ‘1’ if a Read operation is attempted on an
) is valid after the rising edge of the last WE# (or CE#)
Power Up/Down Detection: The Write operation is
status information.
7
and DQ
6
will toggle.
Standard
Program
Standard
Erase
Read from
Erase-
Suspended
Sector/
Block
Read from
Non-Erase-
Suspended
Sector/Block
Program
DD
2
require a valid address when reading
is less than 1.5V.
DQ
DQ
Data
DQ
0
1
6
7
7
7
#
#
to check whether a particular
6
will produce alternating ‘1’s
Toggle
Toggle
Toggle
DQ
Data
1
6
Toggle
Toggle
Toggle
DQ
Data
2
N/A
No
, which can be
2
RY/BY#
6
T1.0 1380
bit will
0
0
1
1
0
6
)
4
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST39VF1602C supports top hardware block protec-
tion, which protects the top 8 KWord block of the device.
The SST39VF1601C supports bottom hardware block pro-
tection, which protects the bottom 8KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 8 KWord when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
TABLE 2: Boot Block Address Ranges
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
required after RST# is driven high before a valid Read can
take place (see Figure 18).
The Erase or Program operation that has been interrupted
needs to be re-initiated after the device resumes normal
operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF1601C/1602C provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
7 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
Product
Bottom Boot Block
Top Boot Block
SST39VF1601C
SST39VF1602C
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
RP ,
any in-progress operation will terminate and
FE000H - FFFFFH
00000H - 01FFFH
Address Range
S71380-04-000
T2.0 1380
RHR
05/10
is