SP706CU-L Exar Corporation, SP706CU-L Datasheet - Page 9
![Low Power Microprocessor Supervisory Circuits](/photos/28/69/286929/8-soic_sml.jpg)
SP706CU-L
Manufacturer Part Number
SP706CU-L
Description
Low Power Microprocessor Supervisory Circuits
Manufacturer
Exar Corporation
Type
Simple Reset/Power-On Resetr
Datasheet
1.SP706EN-L.pdf
(17 pages)
Specifications of SP706CU-L
Number Of Voltages Monitored
1
Reset
Active Low
Reset Timeout
140 ms Minimum
Voltage - Threshold
4.4V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
The SP705-708/813L series provides four key
functions:
1. A reset output during power-up, power-
down and brownout conditions.
2. An independent watchdog output that goes
LOW if the watchdog input has not been
toggled within 1.6 seconds.
3. A 1.25V threshold detector for power-fail
warning, low battery detection, or monitoring
a power supply other than +5V.
4. An active-LOW manual-reset that allows
RESET to be triggered by a pushbutton switch.
The SP707/708 devices are the same as the
SP705/706 devices except for the active-HIGH
RESET substitution of the watchdog timer. The
SP813L is the same as the SP705 except an
active-HIGH RESET is provided rather than an
active-LOW
devices generate a reset when the supply
voltage drops below 4.65V. The SP706/708
devices generate a reset below 4.40V.
The SP705-708/813L series is ideally suited
for
intelligent instruments, and battery-powered
computers
708/813L
environments
supply to a µP and its related components is
critical.
THEORY OF OPERATION
The
microprocessor (µP) supervisory circuit that
monitors the power supplied to digital circuits
such as microprocessors, microcontrollers, or
memory. The series is an ideal solution for
portable,
requires
Implementing
number of components and overall complexity.
The watchdog functions of this product family
will
status of a system. The operational features
and benefits of the SP705-708/813L series are
described in more detail below.
© 2010 Exar Corporation
applications
continuously
SP705-708/813L
battery-powered
series
power
and
RESET.
where
this
controllers.
in
oversee
is
series
The
monitoring
supply
automotive
ideally
series
will
equipment
SP705/707/813L
the
The
reduce
applied
monitoring.
operational
L
L
of
o
o
systems,
w
w
is
SP705-
power
P
P
that
the
o
o
in
w
a
w
9/17
e
e
r
r
M
M
RESET O
A microprocessor's reset input starts the µP in
a known state. The SP705-708/813L series
asserts reset during power-up and prevents
code execution errors during power down or
brownout conditions.
On power-up, once V
a guaranteed logic LOW of 0.4V or less. As V
rises, RESET stays LOW. When V
the reset threshold, an internal timer releases
RESET
whenever V
such as in a brownout condition. When a
brownout condition occurs in the middle of a
previously initiated reset pulse, the pulse
continues for at least another 140ms. On
power down, once V
threshold,
guaranteed to be 0.4V or less until V
below 1.1V.
The
output is simply the complement of the RESET
output and is guaranteed to be valid with V
down to 1.1V. Some µPs, such as Intel's
80C51, require an active-HIGH reset pulse.
W
The
monitors the µP's activity. If the µP does not
toggle the watchdog input (WDI) within 1.6
seconds and WDI is not tri-stated, WDO goes
LOW. As long as RESET is asserted or the WDI
input is tri-stated, the watchdog timer will stay
cleared and will not count. As soon as RESET
is released and WDI is driven HIGH or LOW,
the timer will start counting. Pulses as short as
50ns can be detected.
Typically, WDO will be connected to the non-
maskable interrupt input (NMI) of a µP. When
V
go LOW whether or not the watchdog timer
had timed out. Normally this would trigger an
NMI but RESET goes LOW simultaneously and
thus overrides the NMI.
If WDI is left unconnected, WDO can be used
as a low-line output. Since floating WDI
disables the internal timer, WDO goes LOW
only when V
thus functioning as a low-line output.
i
i
CC
c
c
ATCHDOG
r
r
drops below the reset threshold, WDO will
o
o
p
SP707/708/813L
p
SP705/706/813L
r
r
after
o
o
UTPUT
c
c
CC
e
e
CC
S
T
S
RESET
s
s
IMER
P
dips below the reset threshold,
P
s
s
falls below the reset threshold,
200ms.
o
o
7
7
r
r
0
0
S
S
5
5
CC
u
u
CC
stays
-
-
p
p
reaches 1.1V, RESET is
S
S
falls below the reset
e
RESET
e
active-HIGH
P
P
r
r
watchdog
v
7
v
7
i
i
0
0
s
s
LOW
o
o
8
8
CC
r
r
pulses
-
-
y
y
S
S
rises above
C
C
P
P
Rev. 2.0.0
i
and
CC
i
8
8
r
r
c
RESET
c
circuit
1
1
drops
u
u
LOW
3
3
i
i
t
t
CC
CC
L
L
is
s
s