S29GL01GP11TFCR10 Spansion Inc., S29GL01GP11TFCR10 Datasheet - Page 11

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S29GL01GP11TFCR10

Manufacturer Part Number
S29GL01GP11TFCR10
Description
IC 1GIG 3.0V FLASH MEMORY
Manufacturer
Spansion Inc.
Datasheet

Specifications of S29GL01GP11TFCR10

Cell Type
NOR
Density
1Gb
Access Time (max)
110ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
27/26Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
128M/64M
Supply Current
110mA
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S29GL01GP11TFCR10
Manufacturer:
IDT
Quantity:
101
2. Input/Output Descriptions & Logic Symbol
November 17, 2010 S29GL-P_00_A13
Table 2.1
DQ14–DQ0
WP#/ACC
DQ15/A-1
RESET#
Symbol
A25–A0
RY/BY#
BYTE#
WE#
OE#
CE#
V
V
V
NC
CC
SS
IO
identifies the input and output package connections provided on the device.
No Connect
Supply
Supply
Supply
Output
Type
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
D a t a
Address lines for GL01GP
A24–A0 for GL512P
A23–A0 for GL256P,
A22–A0 for GL128P.
Data input/output.
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
Chip Enable.
Output Enable.
Write Enable.
Device Power Supply.
Versatile IO Input.
Ground.
Not connected internally.
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
V
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-
DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in
word configuration and data I/O pins DQ0-DQ15 are active.
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect/Acceleration Input. At V
outermost sectors. At V
unlock bypass mode. Should be at V
up; when unconnected, WP# is at V
S29GL-P MirrorBit
IL
, the device is actively erasing or programming. At High Z, the device is in ready.
S h e e t
Table 2.1 Input/Output Descriptions
®
Flash Family
HH
, accelerates programming; automatically places device in
IH
IH
IL
.
Description
, disables program and erase functions in the
for all other conditions. WP# has an internal pull-
11

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