S25FL128P0XMFI011 Spansion Inc., S25FL128P0XMFI011 Datasheet - Page 11

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S25FL128P0XMFI011

Manufacturer Part Number
S25FL128P0XMFI011
Description
IC 128M CMOS 3V/104MHZ SPI BUS INTERFACE
Manufacturer
Spansion Inc.
Datasheet

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6. Spansion SPI Modes
July 2, 2007 S25FL128P_00_04
A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices:
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for
both modes.
When the bus master is in standby mode, SCK is as shown in
Note
The Write Protect/Accelerated Programming (WP#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0)
as appropriate.
Mode 0
Mode 3
CPOL = 0, CPHA = 0 (Mode 0)
CPOL = 1, CPHA = 1 (Mode 3)
SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)
SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)
CS3
SPI Interface with
(CPOL, CPHA) =
Bus Master
(0, 0) or (1, 1)
CPOL
CS2
D a t a
0
1
CS1
CPHA
0
1
S h e e t
Figure 6.1 Bus Master and Memory Devices on the SPI Bus
SCK
SCK
CS#
SO
SI
SO
SI
SCK
( P r e l i m i n a r y )
Figure 6.2 SPI Modes Supported
MSB
CS#
SCK SO SI
S25FL128P
SPI Memory
WP#/ACC
Device
HOLD#
CS#
SCK SO SI
Figure 6.2
SPI Memory
WP#/ACC
Device
for each of the two modes:
HOLD#
MSB
CS#
SCK SO SI
SPI Memory
WP#/ACC
Device
HOLD#
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