PIC32MX575F256HT-80I/PT Microchip Technology, PIC32MX575F256HT-80I/PT Datasheet - Page 5

• Manufacturer Part Number: PIC32MX575F256HT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256HT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. Module: Output Compare
6. Module: SPI
7. Module: UART
© 2010 Microchip Technology Inc.
The Fault input detection is not asynchronous.
There is a 1 to 2 Peripheral Bus (PB) clock delay
between the Fault input assertion and the
shutdown of the appropriate OCMP output pin.
Work around
Ensure that the device driven by the OCMP
module can tolerate this shutdown delay.
Affected Silicon Revisions
The SPIBUSY and SRMT bits assert 1 bit time
before the end of the transaction.
Work around
Firmware must provide a 1 bit time delay between
the assertion of these bits and performing any
operation that requires the transaction to be
complete.
Affected Silicon Revisions
The UxSTA.TXBF bit clears one PB clock cycle
after the interrupt is generated. When using a PB
bus divisor other than 1:1 and polling the UART
transmit interrupt flag with the next instruction
reading the UxSTA.TXBF bit, the result may not
reflect the actual TXBF status.
Work around
There are two possible solutions to this issue:
1.
2.
Affected Silicon Revisions
A0
A0
A0
X
X
X
Only use a PB bus divisor of 1:1.
If firmware is polling the transmit interrupt
flag and the TXBF flag, insert a read of the
UxSTA register between these operations
and discard the result. This read will ensure
the status of the TXBF flag is correct when
the next read of this register occurs.
PIC32MX575/675/695/775/795
8. Module: USB
9. Module: Output Compare
10. Module: Output Compare
11. Module: DMA
When U1CNFG1.USBSIDL is set, the USBPLL
does not automatically suspend in Idle mode.
Work around
Use firmware to manually suspend the USB clock
before entering Sleep mode.
Affected Silicon Revisions
In PWM mode, the output waveform is one PB
clock longer than the expected value.
Work around
Load OCRS with a value one less than the number
expected to achieve the desired output.
Affected Silicon Revisions
In PWM mode, if firmware attempts to clear the
OCFLT bit while the Fault still exists, a second
interrupt will not be generated for this Fault when
firmware exits the Interrupt Service Routine (ISR).
The OCFLT bit will remain set while a Fault is
detected.
Work around
In the ISR, clear the OSxFLT bit, and test the
OCxFLT bit before exiting the ISR. If the bit is set,
set the OCx interrupt to generate a second
interrupt.
Affected Silicon Revisions
In Pattern Match mode, the DMA module may not
append all of the CRC results to the result buffer.
Work around
Use firmware to read the CRC result and append
it to the result buffer.
Affected Silicon Revisions
A0
A0
A0
A0
X
X
X
X
DS80480E-page 5