PIC32MX320F128LT-80I/BG Microchip Technology, PIC32MX320F128LT-80I/BG Datasheet - Page 97

• Manufacturer Part Number: PIC32MX320F128LT-80I/BG
• Description: 128 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX320F128LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Processor Series: PIC32MX3xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.0
The PIC32MX Direct Memory Access (DMA) controller
is a bus master module useful for data transfers
between different devices without CPU intervention.
The source and destination of a DMA transfer can be
any of the memory mapped modules existent in the
PIC32MX (such as Peripheral Bus (PBUS) devices:
SPI, UART, I
Following are some of the key features of the DMA
controller module:
• Four Identical Channels, each featuring:
FIGURE 10-1:
© 2010 Microchip Technology Inc.
- Auto-Increment Source and Destination
- Source and Destination Pointers
- Memory to Memory and Memory to
INT Controller
Note 1: This data sheet summarizes the features
Peripheral Bus
Address Registers
Peripheral Transfers
2: Some registers and associated bits
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 31. “Direct Memory
Access (DMA) Controller” (DS61117) of
the “PIC32MX Family Reference Man-
ual”, which is available from the Microchip
web site (www.microchip.com/PIC32).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
2
C™, etc.) or memory itself.
Global Control
(DMACON)
DMA BLOCK DIAGRAM
Address
Decoder
System IRQ
Channel 0
Channel 1
Channel n
Control
Control
Control
• Automatic Word-Size Detection:
• Fixed Priority Channel Arbitration
• Flexible DMA Channel Operating Modes:
• Flexible DMA Requests:
• Multiple DMA Channel Status Interrupts:
• DMA Debug Support Features:
• CRC Generation Module:
Channel Priority
- Transfer Granularity, down to byte level
- Bytes need not be word-aligned at source
- Manual (software) or automatic (interrupt)
- One-Shot or Auto-Repeat Block Transfer
- Channel-to-channel chaining
- A DMA request can be selected from any of
- Each channel can select any (appropriate)
- A DMA transfer abort can be selected from
- Pattern (data) match transfer termination
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half-full
- DMA transfer aborted due to an external
- Invalid DMA address generated
- Most recent address accessed by a DMA
- Most recent DMA channel to transfer data
- CRC module can be assigned to any of the
- CRC module is highly configurable
Arbitration
I
I
I
I
and destination
DMA requests
modes
the peripheral interrupt sources
observable interrupt as its DMA request
source
any of the peripheral interrupt sources
event
channel
available channels
0
1
2
n
PIC32MX3XX/4XX
Y
Interface
Bus
Device Bus + Bus Arbitration
DS61143G-page 97