PIC32MX320F128LT-80I/BG Microchip Technology, PIC32MX320F128LT-80I/BG Datasheet - Page 56

• Manufacturer Part Number: PIC32MX320F128LT-80I/BG
• Description: 128 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX320F128LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Processor Series: PIC32MX3xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX
TABLE 19-3:
TABLE 19-4:
DS61145G-page 56
bit 7
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
ETAP_ADDRESS
ETAP_DATA
ETAP_CONTROL
ETAP_EJTAGBOOT
ETAP_FASTDATA
CPS
Command
CPS: Code-Protect State bit
0 = Device is code-protected
1 = Device is NOT code-protected
Unimplemented: Read as ‘0’
CFGRDY: Code-Protect State bit
0 = Configuration has not been read
1 = Configuration has been read and CP is valid
FCBUSY: Flash Controller Busy bit
0 = Flash Controller is Not Busy (either erase has not started or it has finished)
1 = Flash Controller is Busy (Erase is in progress)
FAEN: Flash Access Enable bit
This bit reflects the state of CFGCON.FAEN.
0 = Flash access is disabled (i.e., processor accesses are blocked)
1 = Flash access is enabled
DEVRST: Device Reset State bit
0 = Device Reset is NOT active
1 = Device Reset is active
MCHP STATUS VALUE
EJTAG TAP INSTRUCTIONS
0
Value
5’h0A
5’h0C
5’h0E
0
5’h08
5’h09
Select Address register.
Select Data register.
Select EJTAG Control register.
Set EjtagBrk, ProbEn and ProbTrap to ‘1’ as Reset value.
Selects the Data and Fastdata registers.
0
CFGRDY
FCBUSY
Description
© 2010 Microchip Technology Inc.
FAEN
DEVRST
bit 0