PIC24HJ32GP302-E/MM Microchip Technology, PIC24HJ32GP302-E/MM Datasheet - Page 211
![16 Bit MCU 40MIPS 32 KB FLASH 28 QFN-S 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24HJ32GP302-E/MM
Manufacturer Part Number
PIC24HJ32GP302-E/MM
Description
16 Bit MCU 40MIPS 32 KB FLASH 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
Specifications of PIC24HJ32GP302-E/MM
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP302-ISO PDF datasheet #2
- PIC24HJ32GP302-ISO PDF datasheet #3
- PIC24HJ32GP302-ISO PDF datasheet #4
- Current page: 211 of 368
- Download datasheet (5Mb)
REGISTER 19-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK STANDARD IDENTIFIER
REGISTER 19-21: CiRXMnEID: ECAN™ ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-5
bit 4
bit 3
bit 2
bit 1-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
R/W-x
SID10
R/W-x
R/W-x
EID15
R/W-x
SID2
EID7
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
SID<10:0>: Standard Identifier bits
1 = Include bit SIDx in filter comparison
0 = Bit SIDx is don’t care in filter comparison
Unimplemented: Read as ‘0’
MIDE: Identifier Receive Mode bit
1 = Match only message types (standard or extended address) that correspond to EXIDE bit in filter
0 = Match either standard or extended address message if filters match
Unimplemented: Read as ‘0’
EID<17:16>: Extended Identifier bits
1 = Include bit EIDx in filter comparison
0 = Bit EIDx is don’t care in filter comparison
EID<15:0>: Extended Identifier bits
1 = Include bit EIDx in filter comparison
0 = Bit EIDx is don’t care in filter comparison
R/W-x
R/W-x
R/W-x
EID14
R/W-x
SID9
SID1
(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))
EID6
REGISTER n (n = 0-2)
REGISTER n (n = 0-2)
C = Writeable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
‘1’ = Bit is set
C = Writeable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
‘1’ = Bit is set
R/W-x
R/W-x
R/W-x
EID13
R/W-x
SID8
SID0
EID5
R/W-x
R/W-x
EID12
R/W-x
SID7
EID4
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-x
R/W-x
R/W-x
EID11
R/W-x
MIDE
SID6
EID3
R/W-x
R/W-x
EID10
R/W-x
SID5
EID2
U-0
—
x = Bit is unknown
x = Bit is unknown
R/W-x
R/W-x
EID17
R/W-x
R/W-x
SID4
EID9
EID1
DS70293E-page 211
R/W-x
R/W-x
EID16
R/W-x
R/W-x
SID3
EID8
EID0
bit 8
bit 0
bit 8
bit 0
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