PIC24HJ32GP202-E/MM Microchip Technology, PIC24HJ32GP202-E/MM Datasheet - Page 2

• Manufacturer Part Number: PIC24HJ32GP202-E/MM
• Description: 16-bit MCU, 32KB Flash,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ32GP202-E/MM

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. I
12. Product Identification
13. UART (UxE Interrupt)
14. UART Module
15. Internal Voltage Regulator
16. PSV Operations
17. I
18. I
19. I
The following sections describe the errata and work
around to these errata, where they may apply.
DS80339D-page 2
When the I
addressing using the same address bits (A10 and
A9) as other I
work as expected.
Revision A2 devices marked as extended temper-
ature range (E) devices, support only industrial
temperature range (I).
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
When the UART module is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA
decoder (IREN = 1), the module incorrectly
transmits a data payload of 80h as 00h.
When the VREGS (RCON<8>) bit is set to a logic
‘0’ higher sleep current may be observed.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
With the I
external
associated with SCL and SDA pins will not reflect
the actual digital logic levels on the pins.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
Least Significant bits (LSbs) of the address are the
same as the 7-bit reserved addresses.
2
2
2
2
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
C Module: 10-bit Addressing Mode
2
Interrupt
C module enabled, the PORT bits and
2
2
C module is configured as a 10-bit
C module is configured for 10-bit
2
C device A10 and A9 bits may not
Input
functions
®
encoder/
(if
any)
1. Module: JTAG Programming
2. Module: UART
3. Module: UART
4. Module: UART
5. Module: UART
JTAG programming does not work.
Work around
None.
The auto-baud feature may not calculate the
correct baud rate when the High Baud Rate Enable
bit, BRGH, is set. With the BRGH bit set, the baud
rate calculation used is the same as BRG = 0.
Work around
If the auto-baud feature is needed, use the Low
Baud Rate mode by clearing the BRGH bit.
With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
Work around
To prevent the Sync Break character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
The auto-baud feature may miscalculate for
certain baud rate and clock speed combinations,
resulting in a BRG value that is greater than or less
than the expected value by 1. This may result in
reception or transmission failures.
Work around
Test the auto-baud rate at various clock speed and
baud rate combinations that would be used in an
application. If an inaccurate BRG value is
generated, manually correct the baud rate in user
software.
When an auto-baud is detected, the receive
interrupt may occur twice. The first interrupt occurs
at the beginning of the Start bit and the second
after reception of the Sync field character.
Work around
If an extra interrupt is detected, ignore the
additional interrupt.
© 2008 Microchip Technology Inc.