PIC24HJ256GP610T-I/PF Microchip Technology, PIC24HJ256GP610T-I/PF Datasheet - Page 16

• Manufacturer Part Number: PIC24HJ256GP610T-I/PF
• Description: 256KB, Flash, 16384bytes-RAM, 40MIPS, 85I/O, 16-bit Family 100 TQFP 14x14x1mm T/
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ256GP610T-I/PF

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b, 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: 3-Wire, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 13
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 32 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24HJXXXGPX06/X08/X10
43. Module: UART
44. Module: SPI
45. Module: I
46. Module: I
47. Module: I
DS80280G-page 16
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an idle state.
Setting the DISSCK bit in the SPIxCON1 register
does not allow the user application to use the SCK
pin as a general purpose I/O pin.
Work around
None.
The BCL bit in I2CSTAT can be cleared only with
16-bit operation and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
Work around
Use 16-bit operations to clear BCL.
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are config-
ured for 10-bit addressing mode, and have the
same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9 should be different.
When the I
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
acknowledges both address bytes.
Work around
None.
2
C devices, the addresses as well as bits
than
2
2
2
2
C
C
C
C module is configured as a 10-bit
0x02;
2
C devices on the bus, one of
however,
the
module
48. Module: I
49. Module: I
50. Module: Internal Voltage Regulator
51. Module: ECAN
With the I
external
associated with the SCL and SDA pins do not
reflect the actual digital logic levels on the pins.
Work around
If the SDA and/or SCL pins need to be polled,
these pins should be connected to other port pins
in order to be read correctly. This issue does not
affect the operation of the I
In 10-bit Addressing mode, some address
matches don't set the RBF flag or load the receive
register I2CxRCV, if the lower address byte
matches the reserved addresses. In particular,
these include all addresses with the form
XX0000XXXX
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
When the VREGS (RCON<8>) bit is set to a logic
‘0’, higher sleep current may be observed.
Work around
Ensure VREGS (RCON<8>) bit is set to a logic ‘1’
for device Sleep mode operation.
The ECAN module does not generate a CAN
event interrupt when coming out of Disable mode
on bus wake-up activity even if the WAKIE bit in
the CiINTE register is set. The WAKIF bit in the
CiINTF register will reflect the correct status. The
CAN event interrupt occurs only if the device was
in Sleep mode when the bus wake-up activity
occurred.
Work around
When placing the ECAN module in Disable mode,
place the device in Sleep mode to be able to
generate the CAN event interrupt on bus wake-up
activity. If it is not possible to place the device in
Sleep mode, poll the WAKIF bit in the CiINTF
register to track bus wake-up activity.
2
interrupt
C module enabled, the PORT bits and
2
2
C
C
and
© 2008 Microchip Technology Inc.
input
XX1111XXXX,
2
C module.
functions
with
(if
any)
the