PIC24HJ12GP202-E/ML Microchip Technology, PIC24HJ12GP202-E/ML Datasheet - Page 137

12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN 6x6mm T

PIC24HJ12GP202-E/ML

Manufacturer Part Number
PIC24HJ12GP202-E/ML
Description
12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN 6x6mm T
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ12GP202-E/ML

Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24HJ12GP202-E/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
16.0
The Inter-Integrated Circuit™ (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
The I
• The SCLx pin is clock
• The SDAx pin is data
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
© 2009 Microchip Technology Inc.
Note:
modes of operation
master and slaves
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
collision and arbitrates accordingly
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7-bit and 10-bit addresses
C Master mode supports 7-bit and 10-bit addresses
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
2
2
C module has a 2-pin interface:
C module offers the following key features:
INTER-INTEGRATED CIRCUIT™
(I
2
This data sheet summarizes the features
of the PIC24HJ12GP201/202 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “PIC24H Family
Reference Manual”, Section 19. “Inter-
Integrated Circuit™ (I
which is available from the Microchip web
site (www.microchip.com).
C)
2
C serial communication
2
C™) module provides
2
2
C™)” (DS70235),
C port can be
Preliminary
PIC24HJ12GP201/202
16.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7-bit and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, refer to the Microchip web site
(www.microchip.com) for the latest “PIC24H Family
Reference Manual” sections.
16.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
• I2CxRSR is the shift register used for shifting data
• I2CxRCV is the receive buffer and the register to
• I2CxTRN is the transmit register to which bytes
• I2CxADD register holds the slave address
• ADD10 status bit indicates 10-bit Address mode
• I2CxBRG acts as the Baud Rate Generator
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
which data bytes are written, or from which data
bytes are read
are written during a transmit operation
(BRG) reload value
2
2
2
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7-bit or 10-bit address
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70282D-page 135

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