PIC24HJ128GP204-E/ML Microchip Technology, PIC24HJ128GP204-E/ML Datasheet - Page 6
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PIC24HJ128GP204-E/ML
Manufacturer Part Number
PIC24HJ128GP204-E/ML
Description
16-bit MCU, 128KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
Specifications of PIC24HJ128GP204-E/ML
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (43K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
11. Module: UART
12. Module: UART
13. Module: Comparator
DS80441F-page 6
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UART error interrupt fails to occur.
Affected Silicon Revisions
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
If CMCON<CxOUTEN> is set and the comparator
module
remappable comparator output pins, C1OUT and
C2OUT, cannot be used as general purpose I/O
pins.
Work around
When the comparator module is disabled the
CMCON<CxOUTEN> bit should be reset so that
the remappable comparator output pins C1OUT
and C2OUT are not driven onto the output pad.
Affected Silicon Revisions
A1
A1
A1
X
X
X
A2
A2
A2
X
X
X
CMCON<CxEN>
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
is
disabled,
the
14. Module: Internal Voltage Regulator
15. Module: PSV Operations
When the VREGS bit (RCON<8>) is set to a logic
‘0’ the device may reset and higher Sleep current
may be observed.
Work around
Ensure VREGS bit (RCON<8>) is set to a logic ‘1’
for device Sleep mode operation.
Affected Silicon Revisions
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
Affected Silicon Revisions
• MOV.D
• Register Indirect Addressing (Word or Byte
A1
A1
X
mode) with pre/post-decrement
X
A2
A2
X
X
A3
A3
X
X
© 2010 Microchip Technology Inc.
A4
A4
X
X