PIC24FV16KA304T-I/MV Microchip Technology, PIC24FV16KA304T-I/MV Datasheet - Page 203

• Manufacturer Part Number: PIC24FV16KA304T-I/MV
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 48 UQFN 6x6x0.5m
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV16KA304T-I/MV

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-48
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 38
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

20.0
FIGURE 20-1:
FIGURE 20-2:
 2011 Microchip Technology Inc.
Note:
Note 1:
Shift Buffer
Data
32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
2:
2 * F
Section
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Cyclic
(DS39729).
Each XOR stage of the shift engine is programmable; see text for details.
Polynomial length n is determined by ([PLEN<3:0>] + 1)
CY
Shift Clock
Redundancy
41.
Family
CRC BLOCK DIAGRAM
CRC SHIFT ENGINE DETAIL
“32-Bit
Bit 0
Reference
Read/Write Bus
Check
Programmable
CRCWDATH
CRCDATH
(4x32, 8x16 or 16x8)
CRC Shift Engine
X(1)
Manual”,
Variable FIFO
(CRC)”
Shift Buffer
(1)
CRCWDATH
0
PIC24FV32KA304 FAMILY
1
Bit 1
CRCWDATL
CRCDATL
LENDIAN
The programmable CRC generator provides a
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in
engine is shown in
up to 32 bits
X(2)
Shift Complete Event
FIFO Empty Event
(1)
Figure
Bit 2
20-1. A simple version of the CRC shift
Figure
CRCWDATL
CRCISEL
20-2.
1
0
X(n)
(1)
Set CRCIF
DS39995B-page 203
Bit n
(2)