PIC24FJ96GA010T-I/PT Microchip Technology, PIC24FJ96GA010T-I/PT Datasheet - Page 16

• Manufacturer Part Number: PIC24FJ96GA010T-I/PT
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ96GA010T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 96KB (32K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core: PIC
• Processor Series: PIC24FJ
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 32 MHz
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 16
• Height: 1 mm
• Interface Type: I2C, SPI, UART
• Length: 12 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2 V
• Width: 12 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ128GA010 FAMILY
56. Module: I
EXAMPLE 1:
DS80471A-page 16
The Transmit Buffer Full (TBF) flag (I2CxSTAT<0>)
may not be cleared by hardware if a collision on the
I
during a transmission.
Work around
None.
Affected Silicon Revisions
2
while(IFS0bits.SPI1IF == 0){}
while(PORTDbits.RD1 == 1){}
SPI1BUF = 0xFF;
C bus occurs before the first falling clock edge
A2
X
A3
X
2
C
A4
X
CHECKING THE STATE OF SPIxIF AGAINST THE SPI CLOCK
C1
C2
//wait for the transmission to complete
//wait for the last clock to finish
//write new data to the buffer
57. Module: SPI (Master Mode)
In Master mode, the SPI Interrupt Flag (SPIxIF)
and the SPIRBF bit (SPIxSTAT<0>) may both
become set one-half clock cycle early, instead of
on the clock edge. This occurs only under the
following circumstances:
• Enhanced Buffer mode is disabled
• the module is configured for serial data output
If the application is using the interrupt flag to deter-
mine when data to be transmitted is written to the
transmit buffer, the data currently in the buffer may
be overwritten.
Work around
Before writing to the SPI buffer, check the SCKx pin
to determine if the last clock edge has passed.
Example 1 (below) demonstrates a method for
doing this. In this example, the RD1 pin functions as
the SPI clock, SCK, which is configured as Idle low.
Affected Silicon Revisions
A2
(SPIBEN = 0); and
changes on transition from clock active to clock
Idle state (CKE = 1)
X
A3
X
A4
X
© 2009 Microchip Technology Inc.
C1
C2