PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 121

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Once the device wakes back up, all I/O pins continue to
maintain their previous states, even after the device
has finished the POR sequence and is executing appli-
cation code again. Pins configured as inputs during
Deep Sleep remain high-impedance and pins config-
ured as outputs continue to drive their previous value.
After waking up, the TRIS and LAT registers, and the
SOSCEN bit (OSCCON<1>) are reset. If firmware
modifies any of these bits or registers, the I/O will not
immediately go to the newly configured states. Once
the firmware clears the RELEASE bit (DSCON<0>) the
I/O pins are “released”. This causes the I/O pins to take
the states configured by their respective TRIS and LAT
bit values.
This means that keeping the SOSC running after
waking up requires the SOSCEN bit to be set before
clearing RELEASE.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR or a true POR event occurs during Deep
Sleep, the I/O pins will be immediately released similar
to clearing the RELEASE bit. All previous state infor-
mation will be lost, including the general purpose
DSGPR0 and DSGPR1 contents.
If a MCLR Reset event occurs during Deep Sleep, the
DSGPRx, DSCON and DSWAKE registers will remain
valid and the RELEASE bit will remain set. The state of
the SOSC will also be retained. The I/O pins, however,
will be reset to their MCLR Reset state. Since
RELEASE is still set, changes to the SOSCEN bit
(OSCCON<1>) cannot take effect until the RELEASE
bit is cleared.
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to
reconfigure the I/O pins.
9.2.4.7
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (CW4<7>). The
device Watchdog Timer (WDT) need not be enabled for
the DSWDT to function. Entry into Deep Sleep mode
automatically resets the DSWDT.
The DSWDT clock source is selected by the
DSWDTOSC
postscaler
DSWDTPS<3:0> Configuration bits (CW4<3:0>). The
minimum time-out period that can be achieved is
2.1 ms and the maximum is 25.7 days. For more
details on the CW4 Configuration register and DSWDT
configuration options, refer to Section 26.0 “Special
Features”.
 2010 Microchip Technology Inc.
options
Deep Sleep WDT
Configuration
are
programmed
bit
(CW4<4>).
by
PIC24FJ64GB004 FAMILY
The
the
9.2.4.8
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC of approximately 5 to 10%. If an
accurate RTCC is required, it must be run from the
SOSC clock source. The RTCC clock source is selected
with the RTCOSC Configuration bit (CW4<5>).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
9.2.4.9
Upon entry into Deep Sleep mode, the status bit,
DPSLP (RCON<10>), becomes set and must be
cleared by software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
• Both the DPSLP and POR bits are cleared. In this
• The DPSLP bit is clear, but the POR bit is set.
• Both the DPSLP and POR bits are set. This
case, the Reset was due to some event other
than a Deep Sleep mode exit.
This is a normal Power-on Reset.
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
Switching Clocks in Deep Sleep Mode
Checking and Clearing the Status of
Deep Sleep Mode
DS39940D-page 121