PIC24FJ64GA106T-I/PT Microchip Technology, PIC24FJ64GA106T-I/PT Datasheet - Page 62
![16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 TQFP 10x10x1mm T/R](/photos/16/13/161322/tqfp64_sml.jpg)
PIC24FJ64GA106T-I/PT
Manufacturer Part Number
PIC24FJ64GA106T-I/PT
Description
16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheet
1.PIC24FJ128GA106-IPT.pdf
(330 pages)
Specifications of PIC24FJ64GA106T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC24FJ256GA110
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
UART, I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Timers
5
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GA106T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 62 of 330
- Download datasheet (3Mb)
PIC24FJ256GA110 FAMILY
EXAMPLE 5-4:
EXAMPLE 5-5:
EXAMPLE 5-6:
DS39905E-page 62
// C example using MPLAB C30
//Set up NVMCON for row programming
//Set up pointer to the first memory location to be written
//Perform TBLWT instructions to write necessary number of latches
// C example using MPLAB C30
asm("DISI #5");
__builtin_write_NVM();
#define NUM_INSTRUCTION_PER_ROW 64
unsigned int offset;
unsigned int i;
unsigned long progAddr = 0xXXXXXX;
unsigned int progData[2*NUM_INSTRUCTION_PER_ROW];
NVMCON = 0x4001;
TBLPAG = progAddr>>16;
offset = progAddr & 0xFFFF;
for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++)
{
}
__builtin_tblwtl(offset, progData[i++]);
__builtin_tblwth(offset, progData[i]);
offset = offset + 2;
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
BTSC
BRA
#5
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
NVMCON, #15
$-2
LOADING THE WRITE BUFFERS (C LANGUAGE CODE)
INITIATING A PROGRAMMING SEQUENCE (ASSEMBLY LANGUAGE CODE)
INITIATING A PROGRAMMING SEQUENCE (C LANGUAGE CODE)
// Block all interrupts with priority < 7
// for next 5 instructions
// Perform unlock sequence and set WR
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
;
;
; and wait for it to be
; completed
// Buffer of data to write
// Write to address low word
// Write to upper byte
// Address of row to write
// Initialize NVMCON
// Initialize PM Page Boundary SFR
// Initialize lower word of address
// Increment address
2010 Microchip Technology Inc.
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