PIC24FJ64GA104T-I/ML Microchip Technology, PIC24FJ64GA104T-I/ML Datasheet - Page 229

16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP 44 QFN 8x8x0.9mm T/R

PIC24FJ64GA104T-I/ML

Manufacturer Part Number
PIC24FJ64GA104T-I/ML
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24FJ64GA104T-I/ML

Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
22.0
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be con-
figured to use any one of four external analog inputs, as
well as voltage reference inputs from the voltage
reference generator and band gap reference.
FIGURE 22-1:
 2010 Microchip Technology Inc.
Note:
C
C
C
CV
C
CV
CCH<1:0>
CREF
X
X
X
X
INB
INC
IND
INA
TRIPLE COMPARATOR
MODULE
REF
REF
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual”,
Comparator Module” (DS39734)
-
+
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
Section
Select
Logic
Input
46.
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
-
+
-
+
-
+
“Scalable
C1
C2
C3
PIC24FJ64GA104 FAMILY
CPOL
EVPOL<1:0>
EVPOL<1:0>
EVPOL<1:0>
CPOL
CPOL
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 22-1. Diagrams of the possible individual
comparator configurations are shown in Figure 22-2.
Each comparator has its own control register,
CMxCON (Register 22-1), for enabling and configuring
its operation. The output and event status of all three
comparators are provided in the CMSTAT register
(Register 22-2).
Trigger/Interrupt
Trigger/Interrupt
Trigger/Interrupt
Logic
Logic
Logic
COE
COE
COE
CEVT
CEVT
COUT
CEVT
COUT
COUT
DS39951C-page 229
C1OUT
C2OUT
C3OUT
Pin
Pin
Pin

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