PIC24FJ64GA004T-I/PT Microchip Technology, PIC24FJ64GA004T-I/PT Datasheet - Page 154

• Manufacturer Part Number: PIC24FJ64GA004T-I/PT
• Description: 64KB, Flash, 8192bytes-RAM, 16MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA004T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164335 - MODULE SKT FOR 10X10 PM3 44TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC24FJ64GA004T-I/PTTR

PIC24FJ64GA004 FAMILY
REGISTER 16-1:
DS39881D-page 154
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
R/W-0
I2CEN
R/W-0
GCEN
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables I2Cx module. All I
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as I
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at
beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave transmission.
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI Support mode is enabled; all addresses Acknowledged
0 = IPMI mode is disabled
A10M: 10-Bit Slave Addressing bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification
0 = Disables SMBus input thresholds
GCEN: General Call Enable bit (when operating as I
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with SCLREL bit.
1 = Enables software or receive clock stretching
0 = Disables software or receive clock stretching
STREN
R/W-0
reception)
U-0
—
I2CxCON: I2Cx CONTROL REGISTER
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
I2CSIDL
ACKDT
R/W-0
R/W-0
2
R/W-0, HC
R/W-1 HC
C™ pins are controlled by port functions.
SCLREL
ACKEN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HC
IPMIEN
R/W-0
RCEN
2
C slave)
2
C Slave)
2
R/W-0, HC
C slave)
R/W-0
A10M
PEN
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0, HC
DISSLW
R/W-0
RSEN
R/W-0, HC
SMEN
R/W-0
SEN
bit 8
bit 0