PIC24FJ48GA004T-I/PT Microchip Technology, PIC24FJ48GA004T-I/PT Datasheet - Page 7

• Manufacturer Part Number: PIC24FJ48GA004T-I/PT
• Description: 16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 TQFP 10x
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ48GA004T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164335 - MODULE SKT FOR 10X10 PM3 44TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14. Module: UART
15. Module: UART
16. Module: UART
 2010 Microchip Technology Inc.
With the auto-baud feature selected, the Sync field
character (0x55) may be loaded into the FIFO as
data.
Work around
To prevent the Sync field character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
Affected Silicon Revisions
The auto-baud may miscalculate for certain baud
rates and clock speed combinations, resulting in a
BRG value that is 1 greater or less than the
expected value. When UxBRG is less than 50, this
can result in transmission and reception failures
due to introducing error greater than 1%.
Work around
Test auto-baud calculations at various clock speed
and baud rate combinations that would be used in
applications. If an inaccurate UxBRG value is
generated, manually correct the baud rate in user
code.
Affected Silicon Revisions
The UART module will not generate consecutive
Break characters. Trying to perform a back-to-
back Break character transmission will cause the
UART module to transmit the dummy character
used to generate the first Break character instead
of transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
A3/
A3/
A3/
A4
A4
A4
X
X
X
B4
B4
B4
X
B5
B5
B5
X
B8
B8
B8
X
PIC24FJ64GA004 FAMILY
17. Module: Output Compare
18. Module: SPI
In PWM mode, the output compare module may
miss a compare event when the current duty cycle
register (OCxRS) value is 0x0000 (0% duty cycle)
and the OCxRS register is updated with a value of
0x0001. The compare event is only missed the first
time a value of 0x0001 is written to OCxRS and the
PWM output remains low for one PWM period.
Subsequent PWM high and low times occur as
expected.
Work around
If the current OCxRS register value is 0x0000,
avoid writing a value of 0x0001 to OCxRS.
Instead, write a value of 0x0002. In this case, how-
ever, the duty cycle will be slightly different from
the desired value.
Affected Silicon Revisions
When using Enhanced Buffer mode, some
indicator bits may be set at incorrect times:
• For slave transfers, the SRMPT bit
• For Slave Interrupt modes (SISELx = 5), there
• There may be several instruction cycle delays
Work around
None at this time.
Affected Silicon Revisions
A3/
A3/
A4
A4
(SPIxSTAT<7>) is set early, after only 7 SCK
periods.
is a one SCK period delay between the
interrupt event and the SPIxIF bit being set.
between the FIFO full or FIFO empty events
and the interrupt flags or indicator bits being
set.
X
X
B4
B4
B5
B5
B8
B8
DS80470E-page 7