PIC24FJ32GA104T-I/ML Microchip Technology, PIC24FJ32GA104T-I/ML Datasheet - Page 205
![16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24FJ32GA104T-I/ML
Manufacturer Part Number
PIC24FJ32GA104T-I/ML
Description
16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24FJ32GA102-ISP.pdf
(308 pages)
2.PIC24FJ32GA102-ISP.pdf
(12 pages)
3.PIC24FJ32GA102-ISP.pdf
(48 pages)
Specifications of PIC24FJ32GA104T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC24FJ32GA102-ISP PDF datasheet
- PIC24FJ32GA102-ISP PDF datasheet #2
- PIC24FJ32GA102-ISP PDF datasheet #3
- Current page: 205 of 308
- Download datasheet (3Mb)
REGISTER 19-3:
2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-10
bit 9-8
bit 7-0
ALRMEN
ARPT7
R/W-0
R/W-0
ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and
0 = Alarm is disabled
CHIME: Chime Enable bit
1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh
0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h
AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29
101x = Reserved; do not use
11xx = Reserved; do not use
ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers.
The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL<15:8>:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVAL<7:0>:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented
ARPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
.
.
.
00000000 = Alarm will not repeat
The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless
CHIME = 1.
CHIME
ARPT6
R/W-0
R/W-0
CHIME = 0)
ALCFGRPT: ALARM CONFIGURATION REGISTER
W = Writable bit
‘1’ = Bit is set
AMASK3
ARPT5
R/W-0
R/W-0
AMASK2
ARPT4
R/W-0
R/W-0
PIC24FJ64GA104 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
AMASK1
ARPT3
R/W-0
R/W-0
AMASK0
ARPT2
R/W-0
R/W-0
th
, once every 4 years)
x = Bit is unknown
ALRMPTR1
ARPT1
R/W-0
R/W-0
DS39951C-page 205
ALRMPTR0
ARPT0
R/W-0
R/W-0
bit 8
bit 0
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