PIC24FJ32GA004T-I/PT Microchip Technology, PIC24FJ32GA004T-I/PT Datasheet - Page 25
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PIC24FJ32GA004T-I/PT
Manufacturer Part Number
PIC24FJ32GA004T-I/PT
Description
32KB, Flash, 8192bytes-RAM, 16MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ32GA004T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164335 - MODULE SKT FOR 10X10 PM3 44TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC24FJ32GA004T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ32GA004T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24FJ32GA004T-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.10
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
The verify process is shown in the flowchart in
Figure 3-8. Memory reads occur a single byte at a time,
so two bytes must be read to compare against the word
in the programmer’s buffer. Refer to Section 3.8
“Reading Code Memory” for implementation details
of reading code memory.
FIGURE 3-8:
© 2008 Microchip Technology Inc.
Note:
Verify Code Memory and
Configuration Word
No
Because
include the device code protection bit,
code memory should be verified immedi-
ately after writing if code protection is
enabled. This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit in
CW1 has been cleared.
with Post-Increment
with Post-Increment
Set TBLPTR = 0
Read High Byte
Read Low Byte
Word = Expect
code memory
verified?
Data?
Does
Done
Start
VERIFY CODE
MEMORY FLOW
the
All
Yes
Yes
Configuration
No
Failure,
Report
Error
registers
3.11
The Application ID Word is stored at address 8005BEh
in executive code memory. To read this memory
location, you must use the SIX control code to move
this program memory location to the VISI register.
Then, the REGOUT control code must be used to clock
the contents of the VISI register out of the device. The
corresponding control and instruction codes that must
be serially transmitted to the device to perform this
operation are shown in Table 3-10.
After the programmer has clocked out the Application
ID Word, it must be inspected. If the Application ID has
the value, BBh, the programming executive is resident
in memory and the device can be programmed using
the mechanism described in Section 4.0 “Device
Programming – Enhanced ICSP”. However, if the
Application ID has any other value, the programming
executive is not resident in memory; it must be loaded
to memory before the device can be programmed. The
procedure for loading the programming executive to
memory is described in Section 5.4 “Programming
the Programming Executive to Memory”.
3.12
Exiting Program/Verify mode is done by removing V
from MCLR, as shown in Figure 3-9. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and program signals on PGCx
and PGDx before removing V
FIGURE 3-9:
PIC24FJXXXGA0XX
MCLR
V
PGDx
PGCx
DD
Reading the Application ID Word
Exiting ICSP Mode
PGD = Input
EXITING ICSP™ MODE
V
P16
IH
IH
.
P17
V
DS39768D-page 25
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