PIC24FJ16GA002T-I/ML Microchip Technology, PIC24FJ16GA002T-I/ML Datasheet - Page 3
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PIC24FJ16GA002T-I/ML
Manufacturer Part Number
PIC24FJ16GA002T-I/ML
Description
16-bit Family, 16 MIPS, 16KB Flash, 4096 Bytes RAM, 21 I/O, NanoWatt 28 QFN 6x6m
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ16GA002T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Details
TABLE 2:
2010 Microchip Technology Inc.
UART
Core
Core
Memory
RTCC
SPI
I
I
I
UART
Oscillator
Voltage
Regulator
Core
SPI
UART
Core
SPI
SPI
SPI
Core
I/O Ports
A/D
Converter
Note 1:
2
2
2
C™
C
C
Module
Only those issues indicated in the last column apply to the current silicon revision.
FIFO Error
Flags
BOR
Instruction
Set
PSV
Master
mode
Master
mode
Slave mode
SOSC
Code-Protect
IrDA
Doze Mode
Master
mode
Master
mode
Framed
modes
Data SRAM
PORTA and
PORTB
SILICON ISSUE SUMMARY (CONTINUED)
Feature
®
—
—
—
—
—
—
Number
Item
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
PERR and FERR not correctly set for all
bytes in receive FIFO.
Spontaneous BOR events with low-range
V
Loop count errors with REPEAT instruction
and R-A-W stalls.
False address error traps at lower boundary
of PSV space.
Decrement of alarm repeat counter under
certain conditions.
SPIIF and SPIBEN may become set early
under certain conditions.
Module may respond to its own master
transmission as a slave under certain
conditions.
Failure to respond correctly to some
reserved addresses in 10-bit mode.
TBF flag not cleared under certain
conditions.
Erroneous sampling and framing errors
when using two Stop bits.
Low-power SOSC unimplemented.
Standby mode not available.
General code protection disables
bootloader functionality.
Interrupts when SPI is operating in
Enhanced Buffer mode.
RXINV bit operation is inverted in IrDA
mode
Instruction execution glitches following
DOZE bit changes.
Spurious transmission and reception of null
data on wake-up from Sleep (Master mode).
Inaccurate SPITBF flag with high clock
divider.
Framed SPI modes not supported.
Higher current consumption during SRAM
operations.
Some I/O pin functions do not work correctly
under certain conditions
Once the A/D module is enabled, it may
continue to draw extra current
DD
.
PIC24FJ64GA004 FAMILY
Issue Summary
®
A3/A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected Revisions
B4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DS80470E-page 3
B5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
B8
X
X
X
X
X
X
X
X
X
X
X
X