PIC24FJ16GA002T-I/ML Microchip Technology, PIC24FJ16GA002T-I/ML Datasheet - Page 158
![16-bit Family, 16 MIPS, 16KB Flash, 4096 Bytes RAM, 21 I/O, NanoWatt 28 QFN 6x6m](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24FJ16GA002T-I/ML
Manufacturer Part Number
PIC24FJ16GA002T-I/ML
Description
16-bit Family, 16 MIPS, 16KB Flash, 4096 Bytes RAM, 21 I/O, NanoWatt 28 QFN 6x6m
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ16GA002T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC24FJ16GA002-ISS PDF datasheet
- PIC24FJ16GA002-ISS PDF datasheet #2
- PIC24FJ16GA002-ISS PDF datasheet #3
- Current page: 158 of 268
- Download datasheet (2Mb)
PIC24FJ64GA004 FAMILY
REGISTER 16-3:
16.5
In both Master and Slave modes, the ACKSTAT bit is
only updated when transmitting data resulting in the
reception of an ACK or NACK from another device. Do
not check the state of ACKSTAT when receiving data,
either as a Slave or a Master. Reading ACKSTAT after
receiving address or data bytes returns an invalid
result.
DS39881D-page 158
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
AMSK7
R/W-0
U-0
—
Acknowledge Status
Unimplemented: Read as ‘0’
AMSK9:AMSK0: Mask for Address Bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match not required in this position
0 = Disable masking for bit x; bit match required in this position
AMSK6
R/W-0
U-0
—
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
W = Writable bit
‘1’ = Bit is set
AMSK5
R/W-0
U-0
—
AMSK4
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
AMSK3
R/W-0
U-0
—
AMSK2
R/W-0
U-0
—
2010 Microchip Technology Inc.
x = Bit is unknown
AMSK9
AMSK1
R/W-0
R/W-0
AMSK8
AMSK0
R/W-0
R/W-0
bit 8
bit 0
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