PIC24F32KA301-E/SS Microchip Technology, PIC24F32KA301-E/SS Datasheet - Page 157
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PIC24F32KA301-E/SS
Manufacturer Part Number
PIC24F32KA301-E/SS
Description
32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 20 SSOP .209in
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.PIC24F16KA301T-ISO.pdf
(320 pages)
Specifications of PIC24F32KA301-E/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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15.2
In Compare mode
module can be configured for single-shot or continuous
pulse generation. It can also repeatedly toggle an
output pin on each timer event.
To set up the module for compare operations:
1.
2.
3.
4.
5.
6.
2011 Microchip Technology Inc.
Calculate the required values for the OCxR and
(for Double Compare modes) OCxRS Duty
Cycle registers:
a)
b)
c)
Write the rising edge value to OCxR and the
falling edge value to OCxRS.
For Trigger mode operations, set OCTRIG to
enable Trigger mode. Set or clear TRIGMODE to
configure trigger operation and TRIGSTAT to
select a hardware or software trigger. For
Synchronous mode, clear OCTRIG.
Set the SYNCSEL<4:0> bits to configure the
trigger or synchronization source. If free-running
timer operation is required, set the SYNCSEL
bits to ‘00000’ (no sync/trigger source).
Select
OCTSEL<2:0> bits. If the desired clock source is
running, set the OCTSEL<2:0> bits before the
output compare module is enabled for proper
synchronization with the desired clock source. If
necessary, set the TON bit for the selected timer
which enables the compare time base to count.
Synchronous mode operation starts as soon as
the synchronization source is enabled; Trigger
mode operation starts after a trigger source event
occurs.
Set the OCM<2:0> bits for the appropriate
compare operation (‘0xx’).
Compare Operations
Determine the instruction clock cycle time.
Take into account the frequency of the
external clock to the timer source (if one is
used) and the timer prescaler settings.
Calculate time to the rising edge of the
output pulse relative to the timer start value
(0000h).
Calculate the time to the falling edge of the
pulse based on the desired pulse width, and
the time to the rising edge of the pulse.
the
time
(Figure
base
15-1), the output compare
source
with
the
PIC24FV32KA304 FAMILY
For 32-bit cascaded operation, these steps are also
necessary:
1.
2.
3.
4.
5.
6.
Depending on the output mode selected, the module
holds the OCx pin in its default state and forces a
transition to the opposite state when OCxR matches
the timer. In Double Compare modes, OCx is forced
back to its default state when a match with OCxRS
occurs. The OCxIF interrupt flag is set after an OCxR
match in Single Compare modes and after each
OCxRS match in Double Compare modes.
Single-shot pulse events only occur once, but may be
repeated by simply rewriting the value of the
OCxCON1 register. Continuous pulse events continue
indefinitely until terminated.
Set
(OCyCON2<8> and (OCxCON2<8>). Enable
the even-numbered module first to ensure the
modules will start functioning in unison.
Clear the OCTRIG bit of the even module
(OCyCON2),
Synchronous mode.
Configure the desired output and Fault settings
for OCy.
Force the output pin for OCx to the output state
by clearing the OCTRIS bit.
If Trigger mode operation is required, configure
the trigger options in OCx by using the OCTRIG
(OCxCON2<7>), TRIGSTAT (OCxCON2<6>)
and SYNCSEL (OCxCON2<4:0>) bits.
Configure the desired Compare or PWM mode
of operation (OCM<2:0>) for OCy first, then for
OCx.
the
OC32
so the module will
bits
for
DS39995B-page 157
both
registers
run
in
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