PIC24F04KA201T-I/SO Microchip Technology, PIC24F04KA201T-I/SO Datasheet - Page 155
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PIC24F04KA201T-I/SO
Manufacturer Part Number
PIC24F04KA201T-I/SO
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SO
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.0
The comparator module provides two dual input
comparators. The inputs to the comparator can be
configured to use any one of four external analog
inputs, as well as a voltage reference input from either
the internal band gap reference divided by 2 (V
the comparator voltage reference generator.
FIGURE 20-1:
© 2009 Microchip Technology Inc.
Note:
CCH<1:0>
CREF
C
V
C
CV
X
BG
X
COMPARATOR MODULE
INB
INA
REF
/2
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Comparator module, refer to the “PIC24F
Family Reference Manual”, Section 19.
“Comparator Module” (DS39710).
COMPARATOR MODULE BLOCK DIAGRAM
Select
Logic
Input
V
V
V
V
IN
IN
IN
IN
-
+
-
+
C1
C2
BG
/2) or
Preliminary
PIC24F04KA201 FAMILY
EVPOL<1:0>
EVPOL<1:0>
CPOL
CPOL
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module is displayed in
Figure 20-1. Diagrams of the possible individual
comparator
Figure 20-2.
Each comparator has its own control register,
CMxCON (Register 20-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 20-2).
Trigger/Interrupt
Trigger/Interrupt
Logic
Logic
configurations
COE
COE
CEVT
CEVT
COUT
COUT
are
DS39937B-page 153
C1OUT
C2OUT
displayed
Pin
Pin
in
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