PIC18LF45K80T-I/PT Microchip Technology, PIC18LF45K80T-I/PT Datasheet - Page 367
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU, NanoWatt XLP 44 TQFP 10x10](/photos/16/13/161303/tqfp44_sml.jpg)
PIC18LF45K80T-I/PT
Manufacturer Part Number
PIC18LF45K80T-I/PT
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU, NanoWatt XLP 44 TQFP 10x10
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18LF45K80T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18LF45K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF45K80T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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23.2.2
The ADRESH:ADRESL register pair is where the 12-bit
A/D result and extended sign bits (ADSGN) are loaded
at the completion of a conversion. This register pair is
16 bits wide. The A/D module gives the flexibility of left
or right justifying the 12-bit result in the 16-bit result
register. The A/D Format Select bit (ADFM) controls
this justification.
FIGURE 23-3:
REGISTER 23-4:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
ADRES11
R/W-x
Result bits
A/D RESULT REGISTERS
ADRES<11:4>: A/D Result High Byte bits
ADRES10
R/W-x
A/D RESULT JUSTIFICATION
Left Justified
ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0)
ADFM = 0
ADSGN bits
ADRESH
W = Writable bit
‘1’ = Bit is set
ADRES9
R/W-x
ADRESL
ADRES8
R/W-x
Preliminary
12-Bit Result
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
ADRES7
R/W-x
Figure 23-3
fication and location of the extended sign bits
(ADSGN). The extended sign bits allow for easier
16-bit math to be performed on the result.
When the A/D Converter is disabled, these 8-bit
registers can be used as two, general purpose registers.
ADRESH
shows the operation of the A/D result justi-
ADRES6
R/W-x
x = Bit is unknown
ADRES5
R/W-x
ADRESL
Right Justified
ADFM = 1
DS39977C-page 367
2010 _18_0001
ADRES4
R/W-x
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