PIC18LF43K22T-I/MV Microchip Technology, PIC18LF43K22T-I/MV Datasheet - Page 131
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PIC18LF43K22T-I/MV
Manufacturer Part Number
PIC18LF43K22T-I/MV
Description
8KB, Flash, 512bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F26J13-ISS.pdf
(496 pages)
Specifications of PIC18LF43K22T-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Number Of Programmable I/os
36
Number Of Timers
1 x 8-bit, 3 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.8
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared by software in the Interrupt
Service Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE/GIEH, is set, the processor
will branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the interrupt priority bits, INT1IP
and INT2IP of the INTCON3 register. There is no prior-
ity bit associated with INT0. It is always a high priority
interrupt source.
EXAMPLE 9-1:
2010 Microchip Technology Inc.
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTn Pin Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
Preliminary
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
9.9
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the INTCON register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP of the INTCON2 register.
See
on the Timer0 module.
9.10
An input change on PORTB<7:4> sets flag bit, RBIF of
the INTCON register. The interrupt can be enabled/
disabled by setting/clearing enable bit, RBIE of the
INTCON register. Pins must also be individually
enabled with the IOCB register. Interrupt priority for
PORTB interrupt-on-change is determined by the value
contained in the interrupt priority bit, RBIP of the
INTCON2 register.
9.11
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see
“Fast Register
WREG, STATUS and BSR registers on entry to the
Interrupt Service Routine. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1
and BSR registers during an Interrupt Service Routine.
PIC18(L)F2X/4XK22
Section 11.0 “Timer0 Module”
TMR0 Interrupt
PORTB Interrupt-on-Change
Context Saving During Interrupts
saves and restores the WREG, STATUS
Stack”), the user may need to save the
DS41412D-page 131
for further details
Section 5.1.3
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