PIC18LF14K22T-I/ML Microchip Technology, PIC18LF14K22T-I/ML Datasheet - Page 108
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PIC18LF14K22T-I/ML
Manufacturer Part Number
PIC18LF14K22T-I/ML
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
Specifications of PIC18LF14K22T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF14K22T-I/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- Current page: 108 of 388
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PIC18F1XK22/LF1XK22
11.2
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF of the PIR1 register. The
interrupt is enabled by setting the TMR2 Match Inter-
rupt Enable bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> of the T2CON register.
FIGURE 11-1:
TABLE 11-1:
DS41365D-page 108
INTCON GIE/GIEH PEIE/GIEL
IPR1
PIE1
PIR1
PR2
TMR2
T2CON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Name
T2OUTPS<3:0>
T2CKPS<1:0>
F
OSC
Timer2 Interrupt
/4
Timer2 Period Register
Timer2 Register
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
TIMER2 BLOCK DIAGRAM
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Internal Data Bus
1:1, 1:4, 1:16
ADIP
ADIE
ADIF
Bit 6
2
Prescaler
TMR0IE
RCIP
RCIE
RCIF
Bit 5
4
TMR2
INT0IE
TXIP
TXIE
Bit 4
TXIF
Preliminary
Reset
8
RABIE
SSPIP
SSPIE
SSPIF
Bit 3
11.3
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode. Addi-
tional information is provided in Section 14.0 “Master
Synchronous Serial Port (MSSP) Module”.
Comparator
1:1 to 1:16
Postscaler
8
TMR2/PR2
Match
Timer2 Output
TMR0IF
CCP1IP
CCP1IE
CCP1IF
Bit 2
TMR2IP
TMR2IE
TMR2IF
INT0IF
2010 Microchip Technology Inc.
Bit 1
PR2
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
TMR1IP
TMR1IE
TMR1IF
RABIF
Bit 0
on page
Values
Reset
257
260
260
260
258
258
258
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