PIC18LF13K22-E/SS Microchip Technology, PIC18LF13K22-E/SS Datasheet - Page 102
![8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 SSOP .209in TU](/photos/16/12/161225/20-ssop_sml.jpg)
PIC18LF13K22-E/SS
Manufacturer Part Number
PIC18LF13K22-E/SS
Description
8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 SSOP .209in TU
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
Specifications of PIC18LF13K22-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F1XK22/LF1XK22
10.1
Timer1 can operate in one of the following modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS of the T1CON register. When TMR1CS is
cleared (= 0), Timer1 increments on every internal
instruction cycle (F
increments on every rising edge of either the Timer1
external clock input or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled, the digital
circuitry associated with the OSC1 and OSC2 pins is
disabled. This means the values of TRISA<5:4> are
ignored and the pins are read as ‘0’.
FIGURE 10-1:
DS41365D-page 102
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
OSC1/T13CKI
Timer1 Operation
Without CLKOUT
OSC2
T1OSCEN
INTOSC
OSC
(1)
Timer1 Oscillator
T1CKPS<1:0>
T1SYNC
TMR1ON
TIMER1 BLOCK DIAGRAM
/4). When the bit is set, Timer1
TMR1CS
(CCP Special Event Trigger)
Clear TMR1
Clock
Internal
F
OSC
/4
Preliminary
On/Off
1
0
Timer1 Clock Input
Prescaler
1, 2, 4, 8
2
TMR1L
Sleep Input
Synchronize
Detect
High Byte
TMR1
2010 Microchip Technology Inc.
1
0
on Overflow
TMR1IF
Set
Timer1
On/Off
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