PIC18F66J93T-I/PT Microchip Technology, PIC18F66J93T-I/PT Datasheet - Page 2
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PIC18F66J93T-I/PT
Manufacturer Part Number
PIC18F66J93T-I/PT
Description
Segmented LCD, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Specifications of PIC18F66J93T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3923 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3923 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
51
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163030
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66J93T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F87J93 FAMILY
TABLE 2:
DS80476A-page 2
MSSP
EUSART
RTCC
MSSP
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
I
Enable/
Disable
INTRC
clock
I
2
2
C™ Slave
C™ Mode
Feature
SILICON ISSUE SUMMARY
Number
Item
1.
2.
3.
4.
If the SSPBUF register is not read within a
window after the SSPIF interrupt, the
module may not receive the correct data.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 T
delay.
The INTRC clock is not automatically
enabled when it is selected.
If a Stop condition occurs in the middle of an
address or data reception, there will be
issues with the SCL clock stream and RCEN
bit.
Issue Summary
CY
© 2009 Microchip Technology Inc.
A1
X
X
X
X
Affected Revisions
(1)