PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

Silicon Errata Issues
1. Module: Reset
2. Module: MSSP (I
 2011 Microchip Technology Inc.
Note:
When a Brown-out Reset (BOR) occurs and the
BOR bit is reset, the Power-on Reset (POR) bit
may also be reset. The resulting state matches
that of the RCON register following a Power-on
Reset event.
Consequently, an application may not be able to
detect whether a BOR or POR event has occurred.
Work around
None.
Affected Silicon Revisions
In extremely rare cases, when configured for
I
not receive the correct data. This occurs only if
the Serial Receive/Transmit Buffer register
(SSPBUF) is not read within a window after the
SSPIF interrupt (PIR<3>) has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPIF bit is set, read the
Affected Silicon Revisions
2
A3
C™ slave reception, the MSSP module may
A3
X
clock stretching feature. This is done by
setting the SEN bit (SSPCON2<0>).
SSPBUF before the first rising clock edge of
the next byte being received.
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A6).
A4
A4
X
X
A5
A5
2
X
X
C slave reception, enable the
2
A6
A6
X
X
C™ Slave)
PIC18F85J11 FAMILY
3. Module: MSSP (I
4. Module: Enhanced Universal
1.
2.
3.
4.
5.
When in I
clock stretching, the first clock pulse after the
slave releases the SCL line may be narrower
than the configured clock width. This may result
in the slave missing the first clock in the next
transmission/reception.
Work around
The clock pulse will be the normal width if the slave
does not perform clock stretching.
Affected Silicon Revisions
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTA<7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2 T
Disable receive interrupts
(RCIE bit, PIE1<5>) = 0).
Disable the EUSART (RCSTA<7> = 0).
Re-enable the EUSART (RCSTA<7> = 1).
Re-enable receive interrupts (PIE1<5> = 1).
(This is the first T
Execute a NOP instruction.
(This is the second T
Affected Silicon Revisions
A3
A3
RCSTA<7> = 0)
X
X
A4
A4
X
X
2
CY
C Master mode, if the slave performs
Synchronous Asynchronous
Receiver Transmitter (EUSART)
delay after re-enabling the EUSART.
A5
A5
X
X
CY
2
delay.)
A6
A6
CY
X
X
C™ Master)
delay.)
DS80383D-page 3