PIC18F46K20-E/MV Microchip Technology, PIC18F46K20-E/MV Datasheet - Page 197

• Manufacturer Part Number: PIC18F46K20-E/MV
• Description: 64KB, Flash, 3968bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

17.3.3
To enable the serial port, SSP Enable bit, SSPEN of
the SSPCON1 register, must be set. To reset or recon-
figure SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
• SCK (Slave mode) must have corresponding
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
 2010 Microchip Technology Inc.
TRIS bit cleared
TRIS bit set
ENABLING SPI I/O
SPI Master SSPM<3:0> = 00xxb
MSb
Serial Input Buffer
Processor 1
SPI MASTER/SLAVE CONNECTION
Shift Register
(SSPBUF)
(SSPSR)
LSb
SDO
SCK
SDI
Serial Clock
17.3.4
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
PIC18F2XK20/4XK20
SDO
SCK
SDI
TYPICAL CONNECTION
SPI Slave SSPM<3:0> = 010xb
MSb
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
Processor 2
LSb
DS41303G-page 197