PIC18F45K20-E/P Microchip Technology, PIC18F45K20-E/P Datasheet - Page 9

• Manufacturer Part Number: PIC18F45K20-E/P
• Description: 32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 PDIP .600in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F24/25/44/45K20
APPENDIX A:
DOCUMENT
REVISION HISTORY
Rev A Document (02/2008)
First revision of this document.
Rev B Document (05/12/08)
Added Module 20: POR, updating subsequent
numbering. Updated Module 5: ADC, Work around
2
description. Added Module 8 MSSP I
C, updating
subsequent numbering. Revised Module 22: Clocks,
added silicon revs.
Rev C Document (08/2008)
Revised Module 22; Added Modules 27 and 28.
Rev D Document (01/2009)
Revised Module 21; Added Module 29.
Rev E Document (05/2009)
Updated Errata to new format; Deleted Module 8:
2
MSSP I
C and Module 23: Comparators; Renumbered
Modules; Added Module 28: ADC; minor edits.
Clarifications/Corrections to the Data Sheet: Added
Module 1: MSSP; Module 2: Electrical Specifications;
Module 3: Electrical Specifications.
Rev F Document (06/2009)
Clarifications/Corrections to the Data Sheet:
Deleted Module 1: MSSP: Figure 17-17 Baud Rate
Generator Block Diagram, updating subsequent num-
bering. Added Module 3 MSSP: Register 17-3
SSPADD; Added Module 4 MSSP: Section 17.4.2
Operation; Added Module 5 MSSP: Figure 17-16
MSSP Block Diagram; Added Module 6 MSSP: Sec-
tions 17.4.7.1, 17.4.8, 17.4.9, 17.4.17.1, 17.4.17.2,
17.4.17.3: SSPADD, changing <6:0> to <7:0>.
Rev G Document (10/2009)
Updated the title of the errata.
Data Sheet Clarifications: Updated the errata deleting
Modules 1, 2, 3, 4, 5, 6.
© 2009 Microchip Technology Inc.
DS80366G-page 9