PIC18F45K20-E/ML Microchip Technology, PIC18F45K20-E/ML Datasheet - Page 3

• Manufacturer Part Number: PIC18F45K20-E/ML
• Description: 32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 44 QFN 8x8x0.9mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: ECCP
2. Module: ECCP
3. Module: MSSP SPI
© 2009 Microchip Technology Inc.
Note:
Changing the CCP1M<3:0> bits of CCP1CON
may cause the CCPR1H and CCPR1L registers to
capture the value of Timer1.
Work around
Halt Timer1 before changing ECCP mode. Reload
Timer1 with desired value after ECCP is setup and
before Timer1 is restarted.
Affected Silicon Revisions
Changing direction in Full-Bridge mode does not
insert dead time between changing the active
drivers in common legs of the bridge.
Work around
None.
Affected Silicon Revisions
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), the first SPI high time
may be short.
Work around
Option 1: Ensure TMR2 value rolls over to zero
Option 2: Turn Timer2 off and clear TMR2 before
Affected Silicon Revisions
A4
A4
A4
X
X
X
This document summarizes all silicon
errata issues from all specified revisions of
silicon.
A7
A7
A7
X
X
X
writing SSPBUF. Enable TMR2 after
SSPBUF is written.
immediately before writing to SSPBUF.
A9
A9
A9
X
X
X
AB
AB
AB
X
X
X
PIC18F24/25/44/45K20
4. Module: MSSP I
5. Module: ADC
6. Module: MSSP I
7. Module: MSSP I
Slew rate is slower than I
the SLRCON<2> bit is set.
Work around
Clear SLRCON<2> bit when using the I
peripheral.
Affected Silicon Revisions
Offset error is 3 LSb typical, 7 LSb maximum,
including
component (~2 LSb).
Work around
The time dependent error is insignificant when the
time between conversions is less than 100 ms.
When the time since the previous conversion is
greater than 100 ms then take two ADC
conversions and discard the first.
Affected Silicon Revisions
If a new address byte is received while the BF flag
is set, the SSPOV bit is properly set and an ACK is
properly not generated. If only the SSPOV bit is set
(BF flag was cleared) and a matching address is
clocked in, that received byte will be improperly
loaded into the SSPBUF register and an ACK will
be improperly generated.
Work around
None.
Affected Silicon Revisions
I
Work around
Use software to emulate Master mode.
Affected Silicon Revisions
2
A4
A4
A4
C Master mode is not functional (Rev. A4 only).
A4
X
X
X
X
A7
A7
A7
A7
X
X
X
an
A9
A9
A9
A9
X
X
X
acquisition
2
2
2
AB
AB
AB
AB
X
X
X
C™
C
C
2
C specifications when
time
DS80366G-page 3
dependent
2
C